ST7LITE20F2 datasheet(101/166 Pages) STMICROELECTRONICS

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On-chip peripherals

Doc ID 8349 Rev 5

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1: Master mode. The function of the SCK pin changes from an input to an output and

the functions of the MISO and MOSI pins are reversed.

●

Bit 3 =

CPOL Clock polarity

This bit is set and cleared by software. This bit determines the idle state of the serial

Clock. The CPOL bit affects both the master and slave modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note:

If CPOL is changed at the communication byte boundaries, the SPI must be disabled by

resetting the SPE bit.

●

Bit 2 =

CPHA Clock Phase

This bit is set and cleared by software.

0: The first clock transition is the first data capture edge.

1: The second clock transition is the first capture edge.

Note:

The slave must have the same CPOL and CPHA settings as the master.

●

Bits 1:0 =

SPR[1:0] Serial Clock Frequency

These bits are set and cleared by software. Used with the SPR2 bit, they select the

baud rate of the SPI serial clock SCK output by the SPI in master mode.

Note:

These 2 bits have no effect in slave mode.

Control/status register (SPICSR)

Read/Write (some bits are Read Only)

Reset Value: 0000 0000 (00h)

●

Bit 7 =

SPIF Serial peripheral data transfer flag (Read only)

This bit is set by hardware when a transfer has been completed. An interrupt is

generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an

access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been cleared.

1: Data transfer between the Device and an external device has been completed.

Table 42.

SPI Master mode SCK frequency

Serial Clock

SPR2

SPR1

SPR0

fCPU/4

fCPU/8

fCPU/16

fCPU/32

fCPU/64

fCPU/128

SPIF

WCOL

OVR

MODF

SOD

SSM

SSI

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