ST7LITE20F2 datasheet(139/166 Pages) STMICROELECTRONICS

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

Electrical characteristics

Doc ID 8349 Rev 5

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Figure 82. Typical VOL vs. VDD (high-sink I/Os)

Figure 83. Typical VDD-VOH vs. VDD

13.9

Control pin characteristics

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

2.4

VDD (V)

-45

0°C

25°C

90°C

130°C

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

2.4

VDD (V)

-45

0°C

25°C

90°C

130°C

0.40

0.50

0.60

0.70

0.80

0.90

1.00

1.10

2.4

2.7

VDD (V)

-45°C

0°C

25°C

90°C

130°C

0.80

0.90

1.00

1.10

1.20

1.30

1.40

1.50

1.60

1.70

1.80

VDD

-45°C

0°C

25°C

90°C

130°C

Table 82.

Asynchronous RESET Pin(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

−

VSS -

0.3

−

0.3xVDD

VIH

Input high level voltage

−

0.7xVD

−

VDD +

0.3

Vhys

Schmitt trigger voltage hysteresis(2)

−−

−

VOL

Output low level voltage(3)

VDD=5V

IIO=+5mA TA≤85°C

TA≥85°C

−

0.5

1.0

1.2

IIO=+2mA TA≤85°C

TA≥85°C

−

0.2

0.4

0.5

RON

Pull-up equivalent resistor(2)(4)

VDD=5V

VDD=3V

120

tw(RSTL)out Generated reset pulse duration

Internal reset sources

−

−μs

th(RSTL)in External reset pulse hold time

(5)

−

−−

μs

tg(RSTL)in Filtered glitch duration

−−

200

−

TA = -40°C to 85°C, unless otherwise specified.

Data based on characterization results, not tested in production.

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