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STLUX385ATR 数据表(PDF) 60 Page - STMicroelectronics |
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STLUX385ATR 数据表(HTML) 60 Page - STMicroelectronics |
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60 / 99 page ![]() Option bytes STLUX385A 60/98 DocID024387 Rev 2 Bit 3: EXTCLK external clock selection: 0: External crystal oscillator clock connected to HseOscin and HseOscout signals 1: External direct drive clock connected to HseOscin Bit 4,2: CKAWUSEL[1:0] AWU clock selection: 00: Low speed internal clock used for AWU module 01: HSE high speed external clock with prescaler used for AWU module 10: Reserved encoding value 11: Reserved encoding value Bit 7-5: RFU reserved; must be kept 0 during register writing for future compatibility nCLKCTL (CKC configuration reg.) nCLKCTL: not(CLKCTL) EMC byte protection. HSESTAB (HSE clock stabilization reg.) Bit 7-0: HSECNT[7:0] HSE crystal oscillator stabilization cycles: 0x00: 2048 clock cycles 0xB4: 128 clock cycles 0xD2: 8 clock cycles 0xE1: 0.5 clock cycles Offset: 0x004808 Default value: 0xF6 (factory configuration) 76 5 4 3 2 1 0 RFU nCKAWUSEL1 nEXTCLK nCKAWUSEL0 nPRSC [1:0] r r/w r/w r/w r/w Offset: 0x004809 Default value: 0x00 76 5432 1 0 HSECNT [7:0] r/w |
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