STLUX385ATR datasheet(29/99 Pages) STMICROELECTRONICS

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STLUX385A

I/O multifunction signal configuration

Several I/Os have multiple functionalities selectable through the configuration mechanism

described in the following sections. The STLUX385A I/Os are grouped into three different

configurable ports: P0, P1 and P2.

5.1

Multifunction configuration policy

The STLUX385A supports either a cold or warm multifunction signal configuration policy

according to the content of the EN_COLD_CFG bit field, part of the GENCFG option byte

When EN_COLD_CFG bit is set, the cold configuration is selected and the multifunction

signals are configured according to the values stored in the option bytes; otherwise when

the EN_COLD_CFG bit is cleared (default case), the warm configuration mode is chosen

and the multifunction pin functionality is configured through the miscellaneous registers.

The configuration options and the proper configuration registers are detailed in the following

table:

The warm configuration is volatile, thus not maintained after a device reset.

5.2

Port P0 I/O multifunction configuration signal

Port P0 multiplexes several input/output functionalities, increasing the device flexibility. The

P0 port pins can be independently assigned to general purpose I/Os or to internal

peripherals. All communication peripherals and the external oscillator are hosted by port P0

pins.

In order to avoid electrical conflicts on the user application board, the P0 signals are

configured at reset as GPIO0[5:0] inputs without pull-up resistors. Once reset is released,

the firmware application must initialize the inputs with the proper configuration according to

the application needs.

Table 3. Multifunction configuration registers

EN_COLD_CFG

Configuration

policy

Multifunction configuration registers

Cold

AFR_IOMXP0, AFR_IOMXP1 and AFR_IOMXP2

0 (default)

Warm

MISC_IOMXP0, MISC_IOMXP1 and MISC_IOMXP2

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