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STLUX385ATR 数据表(PDF) 11 Page - STMicroelectronics |
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STLUX385ATR 数据表(HTML) 11 Page - STMicroelectronics |
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11 / 99 page  DocID024387 Rev 2 11/98 STLUX385A System architecture 2.1 Block diagram Figure 2. Internal block diagram LSI int. Oscillator HSI int. Oscillator Clock Controller Clock controller PowerManagement PLL 96MHz Reset control unit ITC (Interrupt Ctrl) AWU (Auto-wakeup) WWDG (Win. Watchdog) IWDG (Ind. Watchdog) GPIO1 1KB E²PROM Data area 2KB RAM 2KB ROM BootRom System Timer UART DALI 6 Digital input lines SMED0 (PWM0) SWIM & DM (debug module) Internal controller Address and Data Bus I n t. B u s SMED1 (PWM1) SMED2 (PWM2) SMED3 (PWM3) SMED4 (PWM4) SMED5 (PWM5) P 1 I O 32KB FLASH Program area MSC (Misc. registers) MVR POR ResetController MLVD LVD LVR DLVD D HSE ext. Oscillator GPIO0 I 2C 4 Analog Comparators Connection Box P 2 I O ADC – 8 channel P 0 I O |
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