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STLUX385ATR 数据表(PDF) 87 Page - STMicroelectronics |
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STLUX385ATR 数据表(HTML) 87 Page - STMicroelectronics |
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87 / 99 page  DocID024387 Rev 2 87/98 STLUX385A Electrical characteristics 10.3.10 10-bit Sar ADC characteristics Subject to general operating conditions for V DDA , f MASTER , and T A unless otherwise specified. 2. Data based on standard I 2 C protocol requirement, not tested in production. 3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time. 4. I 2 C multifunction signals require the high sink pad configuration and the interconnection of 1 K Ω pull-up resistances. 5. 50 pF is the maximum load capacitance value to meet the I 2 C std timing specifications. Table 52. ADC characteristics Symbol Parameter Conditions Min. Typ. Max. Unit N Resolution 10 bit R ADCIN ADC input impedance 1 M Ω f ADC ADC Clock frequency 1 6 (1) 1. Frequency generated selecting the PLL source clock. MHz V IN1 Conversion voltage range for gain x1 01.25 (2)(3) 2. Maximum input analog voltage cannot exceed V DDA . 3. Exceeding the maximum voltage on the ADCIN[7:0] signals for the related conversion scale must be avoided since the ADC conversion accuracy can be impacted. V IN2 Conversion voltage range for gain x4 0 0.3125 (2)(3) V ref ADC main reference voltage (4) 4. Exceeding the maximum voltage on the ADCIN[7:0] signals for the related conversion scale must be avoided since the ADC conversion accuracy can be impacted. 1.250 V t S Sampling time f ADC = 6 MHz 0.50 μs t STAB Wakeup time from ADC standby 30 t CONV1 Single conversion time including sampling time f ADC = 6 MHz 2.42 t CONV2 Continuous conversion time including sampling time f ADC = 6 MHz 3 |
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