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STLUX385ATR 数据表(PDF) 62 Page - STMicroelectronics |
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STLUX385ATR 数据表(HTML) 62 Page - STMicroelectronics |
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62 / 99 page  Option bytes STLUX385A 62/98 DocID024387 Rev 2 AFR_IOMXP0 (alternative Port0 config. reg.) Bit 5-0: Refer to MSC_IOMXP0 miscellaneous register field description Section 6.2 Bit 7-6: RFU reserved; must be kept 0 during register writing for future compatibility nAFR_IOMXP0 (alternative Port0 config. reg. protect.) nAFR_IOMXP0: not(AFR_IOMXP0) EMC byte protection. AFR_IOMXP1 (alternative Port1 config. reg.) Bit 5-0: Refer to MSC_IOMXP1 miscellaneous register field description Section 6.2.3 Bit 6: RFU reserved; must be kept 0 during register writing for future product compatibility Offset: 0x00480F Default value: 0x00 76 5432 1 0 RFU Sel_p054 [1:0] Sel_p032 [1:0] Sel_p010 [1:0] r r/w r/w r/w Offset: 0x004810 Default value: 0xFF 76 5432 1 0 RFU nSel_p054 [1:0] nSel_p032 [1:0] nSel_p010 [1:0] r r/w r/w r/w Offset: 0x004811 Default value: 0x00 76 5432 1 0 AUXTIM RFU Sel_p15 Sel_p14 Sel_p13 Sel_p12 Sel_p11 Sel_p10 r r r/w r/w r/w r/w r/w r/w |
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