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STLUX385ATR 数据表(PDF) 61 Page - STMicroelectronics |
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STLUX385ATR 数据表(HTML) 61 Page - STMicroelectronics |
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61 / 99 page ![]() DocID024387 Rev 2 61/98 STLUX385A Option bytes nHSESTAB (HSE clock stabilization reg. protect.) nHSESTAB: not(HSESTAB) EMC byte protection. WAITSTATE (Flash wait state reg.) Bit 1-0: Waitstat[1:0] configures the E²PROM and Flash programmable delay read access time: 00: 0 no delay cycle (default case f MASTER @16 MHz) 01: 1 delay cycles 10: 2 delay cycles 11: 3 delay cycles Bit 7-2: RFU reserved; must be kept 0 during register writing for future compatibility nWAITSTATE (Flash wait state reg.) nWAITSTATE: not(WAITSTATE) EMC byte protection. Offset: 0x00480A Default value: 0xFF 76 5432 1 0 nHSECNT [7:0] r/w Offset: 0x00480D Default value: 0x00 76 5432 1 0 RFU Waitstat [1:0] rr/w Offset: 0x00480E Default value: 0xFF 76 5432 1 0 RFU nWaitstat [1:0] rr/w |
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