STLUX385ATR datasheet(64/99 Pages) STMICROELECTRONICS

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Option bytes

STLUX385A

64/98

DocID024387 Rev 2

MSC_OPT0 (misc. config. reg0.)

Bit 2-0:

Bootsel[2:0] boot-rom peripheral enables:

000: Automatic scan boot sources; this selection enables the automatic scan

configuration sequence of all possible initializing peripheral devices: Periph0(UART),

Periph1(RFU), Periph2(RFU).

001: Enable boot source: Periph0

010: Enable boot source: Periph1

011: Enable boot sources: Periph1, Periph0

100: Enable boot source: Periph2

101: Enable boot sources: Periph2, Periph0

110: Enable boot sources: Periph2, Periph1

111: Enable boot sources: Periph2, Periph1, Periph0

Bit 3:

RFU reserved; must be kept 0 during register writing for future compatibility

Bit 5-4:

UARTline[1:0] selects the UART port configuration pins involved during the bootload

sequence in warm configuration mode; in case of cold configuration, this field is

ignored since the UART port is selected by register AFR_IOXP0.

00: Boot sequence with UART i/f configured in all possible UART multiplexed signal

schemes. This sequence is used when UART i/f position is not specified.

01: Boot sequence with UART i/f configured on P0(1,0)

10: Boot sequence with UART i/f configured on P0(3,2)

11: Boot sequence with UART i/f configured on P0(5,4)

Bit 7-6:

RFU reserved; must be kept 0 during register writing for future compatibility

Offset: 0x004815

Default value: 0x00

5432

RFU

UARTline [1:0]

RFU

Bootsel [2:0]

r/w

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