STLUX385ATR datasheet(21/99 Pages) STMICROELECTRONICS

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DocID024387 Rev 2

21/98

STLUX385A

Product overview

3.5.2

Internal 153.6 kHz RC oscillator (LSI)

The low speed internal (LSI) clock is a low speed clock line provided by an internal RC

circuit. It drives both the independent watchdog (IWDG) circuit and the auto-wakeup unit

(AWU). It can also be used as a low power clock line for the master clock f

MASTER

3.5.3

Internal 96 MHz PLL

The PLL provides a high frequency 96 MHz clock used to generate high frequency and

accurate PWM waveforms. The input reference clock must be 16 MHz and may be sourced

either by the internal HSI signal or by the external HSE auxiliary input crystal oscillator line.

The internal PLL prescaled clock cannot be selected as f

MASTER

Note:

Should the end application require a PWM signal with a high degree of stability over long

periods, an external clock source connected to the HSE auxiliary clock line as PLL input

reference clock, should be used. In this case, the external clock source determines the

PWM output stability.

3.5.4

External clock input/crystal oscillator (HSE)

The high speed external clock (HSE) allows the connection of an external clock generated,

for example, by a highly accurate crystal oscillator. The HSE is interconnected with the

MASTER

clock line and to several peripherals. It allows users to provide a custom clock

characterized by a high level of precision and stability to meet the application requirements.

HSE supports two possible external clock sources with a maximum of 24 MHz:

•

crystal/ceramic resonator interconnected with the HseOscin/HseOscout signals

•

direct drive clock interconnected with the HseOscin signal

The HseOscin and HseOscout signals are multifunction pins configurable through the I/O

multiplex mechanism; for further information refer to

Section 5.

Note:

When HSE is configured as fMASTER source clock, the HSE input frequency cannot be

higher than 16 MHz.

When the HSE is the PLL input reference clock, then the HSE input frequency must be

equal to 16 MHz.

If HSE is the reference for the SMED or the ADC logic, the input frequency can be

configured up to 24 MHz.

3.6

Power management

For efficient power management, the application can be put in one of four different low-

power modes. Users can configure each mode to obtain the best compromise between the

lowest power consumption, the fastest startup time and available wakeup sources.

•

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The

wakeup is performed by an internal or external interrupt or reset.

•

Active-halt mode with regulator on: In this mode, the CPU and peripheral clocks are

stopped. An internal wakeup is generated at programmable intervals by the auto-

wakeup unit (AWU). The main voltage regulator is kept powered on, so current

consumption is higher than in active-halt mode with regulator off, but the wakeup time

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