STLUX385ATR datasheet(33/99 Pages) STMICROELECTRONICS

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STLUX385A

I/O multifunction signal configuration

Note:

The P1[5:0] output signals may be read back from the P1_IDR register only when the pins

are configured as GPIO out or PWM signals.

The PWM internal signal is read-back also by the its own SMED through the

SMD<n>_FSM_STS register

5.3.2

P1 programmable pull-up feature

The pad pull-up resistances (47 k

Ω) of Port1 may be configured through the GPIO1 internal

5.4

Port P2 I/O multifunction configuration signal

The Port2 I/O multifunction pins, similarly to Port0 and Port2, can be individually configured

through the following set of registers based on the selected device configuration policy:

•

Cold configuration: AFR_IOMXP2 option byte registers (refer to

Section 8). After reset

the P2 signals are configured in line with AFR_IOMXP2 contents.

•

Warm configuration: MISC_IOMXP2 miscellaneous register (refer to

Section 5.5). After

reset the P2 signals are configured as DIGINs input lines with pull-up enabled.

The following table summarizes the port P2 configurations selected by the register fields

Sel_p25…Sel_p20 which respectively control the bits [5]…[0] of port P2.

Note:

Sel_p254 is a common register field of both registers MSC_IOMXP2 and AFR_IOMXP2.

The peripheral conflict (same resources selected on different pins at the same time) has to

be prevented by SW configuration.

The option byte AFR_IOMXP2 before user configuration by default selects the I2C

alternative functionality.

The signal ports P2[3:1] are exclusively interconnected with DIGIN[3:1] primary pins.

When the I2C i/f is selected on DIGIN[5:4] signals the I/O speed is auto-configured at 10

MHz and the internal pull-up functionality is controlled by the MSC_INPP2AUX1 register.

The P2[0] signal for backward product compatibility is only controlled by field CCOEN of

CKC_CCOR register as shown in the previous table.

Table 6. Port P2 I/O multiplexing signal

Port P2 multifunction configuration signal

Output

signal

Multi-function

signal

Mux Sel

Selection bits

Value (binary)

P2[0]

DIGIN[0]

CCOEN

CCO

P2[4]

DIGIN[4]

Sel_p254

C_sda

P2[5]

DIGIN[5]

Sel_p254

C_scl

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