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STLUX385ATR 数据表(PDF) 30 Page - STMicroelectronics |
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STLUX385ATR 数据表(HTML) 30 Page - STMicroelectronics |
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30 / 99 page  I/O multifunction signal configuration STLUX385A 30/98 DocID024387 Rev 2 5.2.1 Alternate function P0 configuration signals The multifunction pins can be configured via one of the following two registers, depending on the overall configuration policy (warm/cold): • Cold configuration: AFR_IOMXP0 option byte registers (refer to Section 8). After reset the P0 signals are configured in line with AFR_IOMXP0 contents. • Warm configuration: MISC_IOMXP0 miscellaneous register (refer to Section 5.5). After reset, the P0 signals are configured as GPIO input lines with pull-up disabled. The next table summarizes the port P0 configuration scheme. Both registers MSC_IOMXP0 and AFR_IOMXP0 use the same register fields Sel_p054, Sel_p032 and Sel_p010 which respectively control the bits [5,4], [3,2] and [1,0] of port P0. Note: Sel_p054, Sel_p032, Sel_p010 are register fields for both registers MSC_IOMXP0 and AFR_IOMXP0. The peripheral conflict (same resources selected on different pins at the same time) has to be prevented by SW configuration. When the I2C interface is selected either on GPIO0[5:4] or on GPIO0[3:2] signals the related I/O port speed has to be configured at 10 MHz by programming the GPIO0 internal peripheral. 5.2.2 Port P0 diagnostic signals The primary I/Os can be used to trace the SMED's state evolution. This feature allows the debug of the complex SMED configurations. The trace selection can be enabled or disabled via register MSC_IOMXSMD. The diagnostic signal selection through MSC_IOMXSMD register overrides the functional configuration of MSC_IOMXP0 register. Table 4. P0 internal multiplexing signals Port P0 multifunction configuration signal Port pins Multifunction signal Mux sel Selection fields Value (binary) P0[1,0] GPIO0[1] GPIO0[0] Sel_p010 00 UART_rx UART_tx 01 I 2 C_scl I 2 C_sda 10 RFU Reserved encoding 11 P0[3,2] GPIO0[3] GPIO0[2] Sel_p032 00 I 2 C_scl I 2 C_sda 01 HseOscin HseOscout 10 UART_rx UART_tx 11 P0[5,4] GPIO0[5] GPIO0[4] Sel_p054 00 DALI_rx DALI_tx 01 I 2 C_scl I 2 C_sda 10 UART_rx UART_tx 11 |
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