AM79C978VCSLASHW datasheet(178/261 Pages) AMD

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178

Am79C978

S_RESET or setting the STOP

bit.

XMTE

Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. XMTE is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

POWER

Power. When this bit is set to 1,

the device is operating in HIGH

power mode.

RCVE

Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

This bit is always read/write ac-

cessible. RCVE is set to 1 by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

SPEED

Speed. When this bit is set to 1,

the device is operating in HIGH

speed mode.

COLE

Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. COLE is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR49: PHY Select

This register defines which PHY will be able to send

and receive data over the MII interface. Bits 15:8 are

updated whenever the EEPROM is read, and bits 6:0

are updated only if bit 7 is cleared. The bits are defined

as follows:

Bit

Name

Description

PC_NET

PCnet mode. This bit must al-

ways be set.

14-10 RES

Reserved locations. These bits

must be written as zeros.

9-8

PHY_SEL_Default

PHY Select Default. These bits

store the desired default PHY.

These bits have no effect on the

operation of the device and are

provided only as a storage loca-

tion.

PHY_SEL_Lock

PHY Select Lock. Setting this bit

prevents the PHY_SEL bits from

being overwritten by subsequent

soft resets. The user may write

this bit at any time. It is cleared

during Power-On Reset.

6-2

RES

Reserved. Must be written as

zero.

1-0

PHY_SEL

PHY Select. These bits define the

active PHY as follows:

10BASE-T PHY

HomePNA PHY

External PHY

Reserved/Undefined

BCR50-BCR55: Reserved Locations

These registers must be 00h.

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