AM79C978VCSLASHW datasheet(176/261 Pages) AMD

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Am79C978

defined after H_RESET, and is

unaffected by S_RESET and the

STOP bit.

BCR47: OnNow Pattern Matching Register 3

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 is written and the PMAT_MODE bit is 0,

the Pattern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress of the PMR word to be accessed. Following the

write to BCR45, the PMR word may be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

written until the write to BCR47 is complete. The write

to BCR47 causes all 5 bytes (four bytes of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

When PMAT_MODE is 0, the contents of the word ad-

dressed by bits 6:0 of BCR45 can be read by reading

BCR45-47 in any order.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-8

PMR_B4

Pattern Match RAM Byte 4. This

byte is written into or read from

Byte 4 of Pattern Match RAM.

These bits are read and write ac-

cessible always. PMR_B4 is un-

defined after H_RESET, and is

unaffected by S_RESET and the

STOP bit.

7-0

PMR_B3

Pattern Match RAM Byte 3. This

byte is written into or read from

Byte 3 of Pattern Match RAM.

These bits are read and write ac-

cessible always. PMR_B3 is un-

defined after H_RESET, and is

unaffected by S_RESET and the

STOP bit.

BCR48: LED4 Status

This register defines the functionality of LED4. LED4

will default to indicating the selected SPEED with Pulse

stretching enabled (default = 0082h).

BCR48 controls the function(s) that the LED4 pin dis-

plays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabled functions.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED2 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED2 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM PREAD operation.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

LEDOUT

This bit indicates the current

(non-stretched) value of the LED

output pin. A value of 1 in this bit

indicates that the OR of the en-

abled signals is true.

The logical value of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

Read accessible always. This bit

is read only; writes have no ef-

fect. LEDOUT is unaffected by

H_RESET, S_RESET, or STOP.

LEDPOL

LED Polarity. When this bit has

the value 0, then the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals is false (i.e., the LED out-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

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