AM79C978VCSLASHW datasheet(114/261 Pages) AMD

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114

Am79C978

This bit is always read accessi-

ble. INTR is read only. INTR is

cleared by clearing all of the ac-

tive individual interrupt bits that

have not been masked out.

IENA

Interrupt Enable allows INTA to

be active if the Interrupt Flag is

set. If IENA = 0, then INTA will

be disabled regardless of the

state of INTR.

This bit is always read/write ac-

cessible. IENA is set by writing a

1 and cleared by writing a 0. IENA

cleared

H_RESET

S_RESET and setting the STOP

bit.

RXON

Receive On indicates that the re-

ceive function is enabled. RXON

is set if DRX (CSR15, bit 0) is set

to 0 after the START bit is set. If

INIT and START are set together,

RXON will not be set until after

the initialization block has been

read in.

This bit is always read accessi-

ble. RXON is read only. RXON is

cleared

H_RESET

S_RESET and setting the STOP

bit.

TXON

Transmit On indicates that the

transmit

function

enabled.

TXON is set if DTX (CSR15, bit 1)

is set to 0 after the START bit is

set. If INIT and START are set to-

gether, TXON will not be set until

after the initialization block has

been read in.

This bit will reset if the DXSUFLO

bit (CSR3, bit 6) is reset and there

is an underflow condition encoun-

tered.

Read accessible always. TXON

is read only. TXON is cleared by

H_RESET or S_RESET and set-

ting the STOP bit.

TDMD

Transmit Demand, when set,

causes the Buffer Management

Unit to access the Transmit De-

scriptor Ring without waiting for

the poll-time counter to elapse. If

TXON is not enabled, TDMD bit

will be reset and no Transmit De-

scriptor Ring access will occur.

TDMD is required to be set if the

TXDPOLL bit in CSR4 is set. Set-

ting TDMD while TXDPOLL = 0

merely hastens the controller’s

response to a Transmit Descrip-

tor Ring Entry.

This bit is always read/write ac-

cessible. TDMD is set by writing a

1. Writing a 0 has no effect.

TDMD will be cleared by the Buff-

er Management Unit when it

fetches a Transmit Descriptor.

TDMD is cleared by H_RESET or

S_RESET and setting the STOP

bit.

STOP

STOP assertion disables the chip

from all DMA activity. The chip re-

mains inactive until either STRT

or INIT are set. If STOP, STRT,

and INIT are all set together,

STOP will override STRT and

INIT.

This bit is always read/write ac-

cessible. STOP is set by writing a

1, by H_RESET or S_RESET.

Writing a 0 has no effect. STOP is

cleared by setting either STRT or

INIT.

STRT

assertion

enables

the

Am79C978 controller to send and

receive frames and perform buff-

er management operations. Set-

ting STRT clears the STOP bit. If

STRT and INIT are set together,

the Am79C978 controller initial-

ization will be performed first.

This bit is always read/write ac-

cessible. STRT is set by writing a

1. Writing a 0 has no effect. STRT

cleared

H_RESET,

S_RESET, or by setting the

STOP bit.

INIT

assertion

enables

the

Am79C978 controller to begin the

initialization

procedure

which

reads in the initialization block

from memory. Setting INIT clears

the STOP bit. If STRT and INIT

are set together, the Am79C978

controller initialization will be per-

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AM79C978VC/W 数据表(PDF) 114 Page - Advanced Micro Devices

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