AM79C978VCSLASHW datasheet(118/261 Pages) AMD

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118

Am79C978

BSWP bit. Descriptor transfers

are not affected by the setting of

the BSWP bit. RDP, RAP, BDP

and PCI configuration space ac-

cesses are not affected by the

setting of the BSWP bit. Address

PROM transfers and Expansion

ROM accesses are not affected

by the setting of the BSWP bit.

Note that the byte ordering of the

PCI bus is defined to be little En-

dian. BSWP should not be set to

1 when the Am79C978 controller

is used in a PCI bus application.

This bit is always read/write ac-

cessible. BSWP is cleared by

H_RESET or S_RESET and is

not affected by STOP.

1-0

RES

Reserved locations. The default

values of these bits are zeros.

Writing a 1 to this bit has no effect

on device function. If a 1 is written

to these bits, then a 1 will be read

back. Existing drivers may write a

1 to these bits for compatibility,

but new drivers should write a 0

to these bits and should treat the

read value as undefined.

CSR4: Test and Features Control

Certain bits in CSR4 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR4 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

RES

Reserved location. It is OK for

legacy software to write a 1 to this

location. This bit must be set

back to 0 before setting INIT or

STRT bits.

This bit is always read/write ac-

cessible. This bit is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

DMAPLUS

Writing and reading from this bit

has no effect. DMAPLUS is al-

ways set to 1.

RES

Reserved Location. Written as

zero and read as undefined.

TXDPOLL

Disable Transmit Polling. If TXD-

POLL is set, the Buffer Manage-

ment Unit will disable transmit

polling. Likewise, if TXDPOLL is

cleared, automatic transmit poll-

ing is enabled. If TXDPOLL is set,

TDMD bit in CSR0 must be set in

order to initiate a manual poll of a

transmit descriptor. Transmit de-

scriptor polling will not take place

if TXON is reset. Transmit polling

will take place following Receive

activities.

This bit is always read/write ac-

cessible. TXDPOLL is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

APAD_XMT Auto Pad Transmit. When set,

APAD_XMT enables the auto-

matic padding feature. Transmit

frames will be padded to extend

them to 64 bytes including FCS.

The FCS is calculated for the en-

tire frame, including pad, and ap-

pended

after

the

pad

field.

APAD_XMT will override the pro-

gramming of the DXMTFCS bit

(CSR15,

bit

and

the

ADD_FCS bit (TMD1, bit 29).

This bit is always read/write ac-

cessible. APAD_XMT is cleared

by H_RESET or S_RESET and is

unaffected by the STOP bit.

ASTRP_RCV Auto Strip Receive. When set,

ASTRP_RCV enables the auto-

matic pad stripping feature. The

pad and FCS fields will be

stripped from receive frames and

not placed in the FIFO.

This bit is always read/write ac-

cessible. ASTRP_RCV is cleared

by H_RESET or S_RESET and is

unaffected by the STOP bit.

MFCO

Missed Frame Counter Overflow

is set by the Am79C978 control-

ler

when

the

Missed

Frame

Counter (CSR112 and CSR113)

has wrapped around.

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