AM79C978VCSLASHW datasheet(122/261 Pages) AMD

122 / 261 page

122

Am79C978

from where it had left, when it en-

tered the suspend mode.

This bit is always read/write ac-

cessible. SPND is cleared by

H_RESET, S_RESET, or by set-

ting the STOP bit.

CSR6: RX/TX Descriptor Table Length

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-12

TLEN

Contains a copy of the transmit

encoded ring length (TLEN) field

read from the initialization block

during the Am79C978 controller

initialization. This field is written

during the Am79C978 initializa-

tion routine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

TLEN is only defined after initial-

ization. These bits are unaffected

H_RESET,

S_RESET,

STOP.

11-8

RLEN

Contains a copy of the receive

encoded ring length (RLEN) read

from the initialization block during

Am79C978 controller initializa-

tion. This field is written during

the Am79C978 initialization rou-

tine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

RLEN is only defined after initial-

ization. These bits are unaffected

H_RESET,

S_RESET,

STOP.

7-0

RES

Reserved locations. Read as 0s.

Write operations are ignored.

CSR7: Extended Control and Interrupt 2

Certain bits in CSR7 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR7 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

FASTSPNDE

Fast Suspend Enable. When

FASTSPNDE is set to 1, the

Am79C978 controller performs a

fast

suspend

whenever

the

SPND bit is set.

When a fast suspend is request-

ed, the Am79C978 controller per-

forms a quick entry into the

suspend mode. At the time the

SPND bit is set, the Am79C978

controller will complete the DMA

process of any transmit and/or re-

ceive packet that had already be-

gun DMA activity. In addition, any

transmit packet that had started

transmission will be fully transmit-

ted, and any receive packet that

had begun reception will be fully

received. However, no additional

packets will be transmitted or re-

ceived and no additional transmit

or receive DMA activity will begin.

Hence, the Am79C978 controller

may enter the suspend mode

with

transmit

and/or

receive

packets still in the FIFOs or the

SRAM.

When FASTSPNDE is 0 and the

SPND bit is set, the Am79C978

controller may take longer before

entering the suspend mode. At

the time the SPND bit is set, the

Am79C978 controller will com-

plete the DMA process of a trans-

mit packet if it had already begun,

and the Am79C978 controller will

completely

receive

packet if it had already begun.

Additionally, all transmit packets

stored in the transmit FIFOs and

the transmit buffer area in the

SRAM (if one is enabled) will be

transmitted and all receive pack-

ets stored in the receive FIFOs,

and the receive buffer area in the

SRAM (if one is enabled) will be

transferred into system memory.

Since the FIFO and SRAM con-

tents are flushed, it may take

much

longer

before

the

Am79C978 controller enters the

AM79C978VC/W 数据表(PDF) 122 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 122 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载