AM79C978VCSLASHW datasheet(123/261 Pages) AMD

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Am79C978

123

suspend mode. The amount of

time that it takes depends on

many factors including the size of

the SRAM, bus latency, and net-

work traffic level.

When a write to CSR5 is per-

formed with bit 0 (SPND) set to 1,

the value that is simultaneously

written to FASTSPNDE is used to

determine which approach

used to enter suspend mode.

This bit is always read/write ac-

cessible. FASTSPNDE is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

RES

Reserved location.

RDMD

Receive

Demand,

when

set,

causes the Buffer Management

Unit to access the Receive De-

scriptor Ring without waiting for

the receive poll-time counter to

elapse. If RXON is not enabled,

RDMD has no meaning and no

receive Descriptor Ring access

will occur.

RDMD is required to be set if the

RXDPOLL bit in CSR7 is set. Set-

ting RDMD while RXDPOLL = 0

merely hastens the Am79C978

controller’s response to a receive

Descriptor Ring Entry.

This bit is always read/write ac-

cessible. RDMD is set by writing

a 1. Writing a 0 has no effect.

RDMD will be cleared by the Buff-

er Management Unit when it

fetches

receive

Descriptor.

RDMD is cleared by H_RESET.

RDMD

unaffected

S_RESET or by setting the STOP

bit.

RXDPOLL

Receive Disable Polling. If RXD-

POLL is set, the Buffer Manage-

ment Unit will disable receive

polling. Likewise, if RXDPOLL is

cleared, automatic receive poll-

ing is enabled. If RXDPOLL is

set, RDMD bit in CSR7 must be

set in order to initiate a manual

poll of a receive descriptor. Re-

ceive Descriptor Polling will not

take place if RXON is reset.

This bit is always read/write ac-

cessible. RXDPOLL is cleared by

H_RESET. RXDPOLL is unaf-

fected by S_RESET or by setting

the STOP bit.

STINT

Software Timer Interrupt. The

Software Timer interrupt is set by

the Am79C978 controller when

the Software Timer counts down

to 0. The Software Timer will im-

mediately load the STVAL (BCR

31, bits 5-0) into the Software

Timer and begin counting down.

When STINT is set to 1, INTA is

asserted if the enable bit STINTE

is set to 1.

This bit is always read/write ac-

cessible. STINT is cleared by the

host by writing a 1. Writing a 0

has no effect. STINT is cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

STINTE

Software Timer Interrupt Enable.

If STINTE is set, the STINT bit

will be able to set the INTR bit.

This bit is always read/write ac-

cessible. STINTE is set to 0 by

H_RESET and is not affected by

S_RESET or setting the STOP bit

MREINT

PHY Management Read Error In-

terrupt. The PHY Read Error in-

terrupt is set by the Am79C978

controller to indicate that the cur-

rently read register from the PHY

is invalid, the contents of BCR34

are incorrect, and the operation

should be performed again. The

indication of an incorrect read

comes from the internal PHY.

When MREINT is set to 1, INTA is

asserted if the enable bit MREIN-

TE is set to 1.

This bit is always read/write ac-

cessible. MREINT is cleared by

the host by writing a 1. Writing a

0 has no effect. MREINT is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

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