AM79C978VCSLASHW datasheet(127/261 Pages) AMD

127 / 261 page

Am79C978

127

CSR15: Mode

This register’s fields are loaded during the Am79C978

controller initialization routine with the corresponding

Initialization Block values, or when a direct register write

has been performed on this register.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

PROM

Promiscuous

Mode.

When

PROM = 1, all incoming receive

frames are accepted.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

DRCVBC

Disable

Receive

Broadcast.

When

set,

disables

the

Am79C978 controller from re-

ceiving

broadcast

messages.

Used for protocols that do not

support broadcast addressing,

except as a function of multicast.

DRCVBC is cleared by activation

H_RESET

S_RESET

(broadcast messages will be re-

ceived) and is unaffected by

STOP.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

DRCVPA

Disable Receive Physical Ad-

dress. When set, the physical ad-

dress detection (Station or node

ID) of the Am79C978 controller

will be disabled. Frames ad-

dressed to the nodes individual

physical address will not be rec-

ognized.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

12-9

RES

Reserved locations. Written as

zeros and read as undefined.

8-7 PORTSEL[1:0] Port Select bits allow for software

controlled selection of the net-

work medium. The only legal val-

ues for this field is 11.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set. Cleared by

H_RESET or S_RESET and is

unaffected by STOP.

INTL

Internal Loopback. See the de-

scription of LOOP (CSR15, bit 2).

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

DRTY

Disable Retry. When DRTY is set

to 1, the Am79C978 controller will

attempt only one transmission. In

this mode, the device will not pro-

tect the first 64 bytes of frame

data in the Transmit FIFO from

being overwritten, because auto-

matic retransmission will not be

necessary. When DRTY is set to

0, the Am79C978 controller will

attempt 16 transmissions before

signaling a retry error.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

FCOLL

Force Collision. This bit allows

the collision logic to be tested.

The Am79C978 controller must

be in internal loopback for FCOLL

to be valid. If FCOLL = 1, a colli-

sion will be forced during loop-

back

transmission

attempts,

which will result in a Retry Error.

If FCOLL = 0, the Force Collision

logic will be disabled. FCOLL is

defined

after

the

initialization

block is read.

This bit is read/write accessible

only when either the STOP or the

SPND bit is set.

DXMTFCS

Disable Transmit CRC (FCS).

When DXMTFCS is set to 0, the

transmitter will generate and ap-

pend an FCS to the transmitted

frame. When DXMTFCS is set to

1, no FCS is generated or sent

with

the

transmitted

frame.

DXMTFCS is overridden when

ADD_FCS and ENP bits are set

in TMD1.

When the APAD_XMT bit (CSR4,

bit11) is set to 1, the setting of

DXMTFCS has no effect.

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