AM79C978VCSLASHW datasheet(131/261 Pages) AMD

131 / 261 page

Am79C978

131

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR34: Current Transmit Descriptor Address

Lower

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

CXDAL

Contains the lower 16 bits of the

current transmit descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR35: Current Transmit Descriptor Address

Upper

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

CXDAU

Contains the upper 16 bits of the

current transmit descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR36: Next Next Receive Descriptor Address

Lower

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NNRDAL

Contains the lower 16 bits of the

next next receive descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR37: Next Next Receive Descriptor Address

Upper

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NNRDAU

Contains the upper 16 bits of the

next next receive descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR38: Next Next Transmit Descriptor Address

Lower

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NNXDAL

Contains the lower 16 bits of the

next next transmit descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR39: Next Next Transmit Descriptor Address

Upper

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NNXDAU

Contains the upper 16 bits of the

next next transmit descriptor ad-

dress pointer.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR40: Current Receive Byte Count

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

AM79C978VC/W 数据表(PDF) 131 Page - Advanced Micro Devices

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AM79C978VC/W 数据表(PDF) 131 Page - Advanced Micro Devices

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