AM79C978VCSLASHW datasheet(133/261 Pages) AMD

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Am79C978

133

15-0

TXPOLL

Transmit Poll Time Counter. This

counter is incremented by the

Am79C978 controller microcode

and is used to trigger the transmit

descriptor ring polling operation

of the Am79C978 controller.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR47: Transmit Polling Interval

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0 TXPOLLINT

Transmit Polling Interval. This

Am79C978 controller will wait be-

tween successive polling opera-

tions. The TXPOLLINT value is

expressed as the two’s comple-

ment of the desired interval,

where each bit of TXPOLLINT

represents 1 clock period of time.

TXPOLLINT[3:0]

are

ignored.

(TXPOLLINT[16] is implied to be

a one, so TXPOLLINT[15] is sig-

nificant and does not represent

the sign of the two’s complement

TXPOLLINT value.)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods

(1.966

when

CLK = 33 MHz). The TXPOL-

LINT value of 0000h is created

during the microcode initialization

routine and, therefore, might not

be seen when reading CSR47 af-

ter H_RESET or S_RESET.

If the user desires to program a

value for POLLINT other than the

default, then the correct proce-

dure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP (CSR0, bit

2). Then the user may write to

CSR47 and then set STRT in

CSR0. In this way, the default

value of 0000h in CSR47 will be

overwritten with the desired user

value.

If the user does not use the stan-

dard

initialization

procedure

(standard implies use of an initial-

ization block in memory and set-

ting the INIT bit of CSR0), but

instead chooses to write directly

to each of the registers that are

involved in the INIT operation,

then it is imperative that the user

also writes all zeros to CSR47 as

part of the alternative initialization

sequence.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR48: Receive Poll Time Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RXPOLL

Receive Poll Time Counter. This

counter is incremented by the

Am79C978 controller microcode

and is used to trigger the receive

descriptor ring polling operation

of the Am79C978 controller.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR49: Receive Polling Interval

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RXPOLLINT Receive Polling Interval. This reg-

ister contains the time that the

Am79C978 controller will wait be-

tween successive polling opera-

tions. The RXPOLLINT value is

expressed as the two’s comple-

ment of the desired interval,

where each bit of RXPOLLINT

represents

approximately

one

clock

time

period.

RXPOL-

LINT[3:0] are ignored. (RXPOL-

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