AM79C978VCSLASHW datasheet(135/261 Pages) AMD

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Am79C978

135

and is not affected by S_RESET

or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

upper 8 bits of the 32-bit address

bus during master accesses initi-

ated by the Am79C978 controller.

This action is required because

the 16-bit software structures

specified by the SSIZE32 = 0 set-

ting will yield only 24 bits of ad-

dress

for

the

Am79C978

controller bus master accesses.

If SSIZE32 is set, then the soft-

ware structures that are common

to the Am79C978 controller and

the host system will supply a full

32 bits for each address pointer

that is needed by the Am79C978

controller for performing master

accesses.

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress pins are always driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE32 bit has no effect on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0

SWSTYLE

Software Style register. The val-

ue in this register determines the

style of register and memory re-

sources that shall be used by the

Am79C978 controller. The Soft-

ware Style selection will affect the

interpretation of a few bits within

the CSR space, the order of the

descriptor entries and the width of

the descriptors and initialization

block entries.

All Am79C978 controller CSR

bits and BCR bits and all descrip-

tor, buffer, and initialization block

entries not cited in Table 31 are

unaffected by the Software Style

selection and are, therefore, al-

ways fully functional as specified

in the CSR and BCR sections.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. The SW-

STYLE register will contain the

value 00h following H_RESET

and

will

unaffected

S_RESET or STOP.

Table 31.

Software Styles

SWSTYLE

[7:0]

Style

Name

SSIZE32

Initialization Block

Entries

Descriptor Ring Entries

00h

LANCE/PCnet-ISA

controller

16-bit software structures,

non-burst or burst access

16-bit software structures,

non-burst access only

01h

RES

02h

PCnet-PCI

controller

32-bit software structures,

non-burst or burst access

32-bit software structures,

non-burst access only

03h

PCnet-PCI

controller

32-bit software structures,

non-burst or burst access

32-bit software structures,

non-burst or burst access

All Other

RES

Undefined

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