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AM79C978VC/W 数据表(PDF) 136 Page - Advanced Micro Devices |
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AM79C978VC/W 数据表(HTML) 136 Page - Advanced Micro Devices |
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136 / 261 page  136 Am79C978 CSR60: Previous Transmit Descriptor Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 PXDAL Contains the lower 16 bits of the previous transmit descriptor ad- dress pointer. The Am79C978 controller has the capability to stack multiple transmit frames. These bits are read/write acces- sible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR61: Previous Transmit Descriptor Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 PXDAU Contains the upper 16 bits of the previous transmit descriptor ad- dress pointer. The Am79C978 controller has the capability to stack multiple transmit frames. These bits are read/write acces- sible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR62: Previous Transmit Byte Count Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-12 RES Reserved locations. 11-0 PXBC Previous Transmit Byte Count. This field is a copy of the BCNT field of TMD1 of the previous transmit descriptor. These bits are read/write acces- sible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR63: Previous Transmit Status Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 PXST Previous Transmit Status. This field is a copy of bits 31-16 of TMD1 of the previous transmit descriptor. These bits are read/write acces- sible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR64: Next Transmit Buffer Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NXBAL Contains the lower 16 bits of the next transmit buffer address from which the Am79C978 controller will transmit an outgoing frame. These bits are read/write accessi- ble only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR65: Next Transmit Buffer Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NXBAU Contains the upper 16 bits of the next transmit buffer address from which the Am79C978 controller will transmit an outgoing frame. These bits are read/write acces- sible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. |
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