AM79C978VCSLASHW datasheet(132/261 Pages) AMD

132 / 261 page

132

Am79C978

15-12

RES

Reserved locations. Read and

written as zeros.

11-0

CRBC

Current Receive Byte Count.

This field is a copy of the BCNT

field of RMD1 of the current re-

ceive descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR41: Current Receive Status

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

CRST

Current Receive Status. This

field is a copy of bits 31-16 of

RMD1 of the current receive de-

scriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR42: Current Transmit Byte Count

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-12

RES

Reserved locations. Read and

written as zeros.

11-0

CXBC

Current Transmit Byte Count.

This field is a copy of the BCNT

field of TMD1 of the current trans-

mit descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR43: Current Transmit Status

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

CXST

Current Transmit Status. This

field is a copy of bits 31-16 of

TMD1 of the current transmit de-

scriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR44: Next Receive Byte Count

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-12 RES

Reserved locations. Read and

written as zeros.

11-0

NRBC

Next Receive Byte Count. This

field is a copy of the BCNT field of

RMD1 of the next receive de-

scriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR45: Next Receive Status

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NRST

Next Receive Status. This field is

a copy of bits 31-16 of RMD1 of

the next receive descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR46: Transmit Poll Time Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

AM79C978VC/W 数据表(PDF) 132 Page - Advanced Micro Devices

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AM79C978VC/W 数据表(PDF) 132 Page - Advanced Micro Devices

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