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AM79C978VC/W 数据表(PDF) 137 Page - Advanced Micro Devices |
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AM79C978VC/W 数据表(HTML) 137 Page - Advanced Micro Devices |
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137 / 261 page  Am79C978 137 CSR66: Next Transmit Byte Count Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-12 RES Reserved locations. Read and written as zeros. 11-0 NXBC Next Transmit Byte Count. This field is a copy of the BCNT field of TMD1 of the next transmit de- scriptor. These bits are read/write acces- sible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR67: Next Transmit Status Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NXST Next Transmit Status. This field is a copy of bits 31-16 of TMD1 of the next transmit descriptor. These bits are read/write acces- sible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. 7-0 RES Reserved locations. Read and written as zeros. Accessible only when either the STOP or the SPND bit is set. CSR72: Receive Ring Counter Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 RCVRC Receive Ring Counter location. Contains a two’s complement bi- nary number used to number the current receive descriptor. This counter interprets the value in CSR76 as pointing to the first de- scriptor. A counter value of zero corresponds to the last descriptor in the ring. These bits are read/write acces- sible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR74: Transmit Ring Counter Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 XMTRC Transmit Ring Counter location. Contains a two’s complement bi- nary number used to number the current transmit descriptor. This counter interprets the value in CSR78 as pointing to the first de- scriptor. A counter value of zero corresponds to the last descriptor in the ring. These bits are read/write acces- sible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR76: Receive Ring Length Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 RCVRL Receive Ring Length. Contains the two’s complement of the re- ceive descriptor ring length. This register is initialized during the Am79C978 controller’s initializa- tion routine based on the value in the RLEN field of the initialization block. However, this register can be manually altered. The actual receive ring length is defined by the current value in this register. The ring length can be defined as any value from 1 to 65535. These bits are read/write acces- sible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. |
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