AM79C978VCSLASHW datasheet(141/261 Pages) AMD

141 / 261 page

Am79C978

141

DMABC register is undefined un-

til written.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR88: Chip ID Register Lower

Bit

Name

Description

31-28 VER

Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. Write opera-

tions are ignored.

27-12 PARTID

Part number. The 16-bit code for

the

Am79C978

controller

0010 0110 0010 0110 (2626h).

This register is exactly the same

as the Device ID register in the

JTAG description. However, this

part number is different from that

stored in the Device ID register in

the PCI configuration space.

Read accessible only when either

the STOP or the SPND bit is set.

PARTID is read only. Write oper-

ations are ignored.

11-1

MANFID

Manufacturer ID. The 11-bit man-

ufacturer

code

for

AMD

00000000001b. This code is per

the JEDEC Publication 106-A.

Note that this code is not the

same as the Vendor ID in the PCI

configuration space.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. MANFID is

read only. Write operations are

ignored.

ONE

Always a logic 1.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. ONE is read

only. Write operations are ig-

nored.

CSR89: Chip ID Register Upper

Bit

Name

Description

31-16 RES

Reserved locations. Read as un-

defined.

15-12 VER

Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. Write opera-

tions are ignored.

11-0

PARTIDU

Upper 12 bits of the Am79C978

controller part number, i.e., 0010

0110 0010b (262h).

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. PARTIDU is

read only. Write operations are

ignored.

CSR92: Ring Length Conversion

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RCON

Ring Length Conversion Regis-

ter. This register performs a ring

length conversion from an encod-

ed value as found in the initializa-

tion block to a two’s complement

value used for internal counting.

By writing bits 15-12 with an en-

coded ring length, a two’s com-

plemented value is read. The

RCON register is undefined until

written.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR100: Bus Timeout

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

MERRTO

This register contains the value of

the longest allowable bus latency

(interval between assertion of

REQ and assertion of GNT) that a

AM79C978VC/W 数据表(PDF) 141 Page - Advanced Micro Devices

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