AM79C978VCSLASHW datasheet(143/261 Pages) AMD

143 / 261 page

Am79C978

143

PMAT

Pattern Matched. This bit is set

when the PMMODE bit is set and

an OnNow pattern match occurs.

PMAT is cleared when power is

initially applied (POR).

This bit is read accessible al-

ways.

EMPPLBA

Magic Packet Physical Logical

Broadcast Accept. If both EMP-

PLBA and MPPLBA (CSR5, bit 5)

are at their default value of 0, the

Am79C978 controller will only de-

tect a Magic Packet frame if the

destination address of the packet

matches the content of the physi-

cal address register (PADR). If ei-

ther EMPPLBA or MPPLBA is set

to 1, the destination address of

the Magic Packet frame can be

unicast, multicast, or broadcast.

Note that the setting of EMPPL-

BA and MPPLBA only affects the

address detection of the Magic

Packet frame. The Magic Packet

frame’s data sequence must be

made up of 16 consecutive phys-

ical addresses (PADR[47:0]) re-

gardless

what

kind

destination address it has.

This bit is always read/write ac-

cessible. EMPPLBA is set to 0 by

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

MPMAT

Magic Packet Match. This bit is

set when the integrated Ethernet

controller detects a Magic Packet

while it is in Magic Packet mode.

MPMAT is cleared when power is

initially applied (POR).

This bit is always read/write ac-

cessible.

MPPEN

Magic Packet Pin Enable. When

this bit is set, the device enters

the Magic Packet mode when the

PG input goes LOW or MPEN bit

(CSR5, bit 2) gets set to 1. This

bit is OR’ed with MPEN bit

(CSR5, bit 2).

Read/Write accessible only when

either the STOP bit or the SPND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

3-1

RES

Reserved locations.

RST_POL

PHY_RST Pin Polarity. If the

PHY_POL

set

the

PHY_RST pin is active LOW; oth-

erwise PHY_RST is active HIGH.

This bit is read/write accessible

only when either the STOP bit or

the SPND bit is set. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

CSR122: Advanced Feature Control

Bit

Name

Description

31-1

RES

Reserved locations. Written as

zeros and read as undefined.

RCVALGN

Receive Packet Align. When set,

this bit forces the data field of ISO

8802-3 (IEEE/ANSI 802.3) pack-

ets to align to 0 MOD 4 address

boundaries (i.e., DWord aligned

addresses). It is important to note

that this feature will only function

correctly if all receive buffer

boundaries are DWord aligned

and all receive buffers have 0

MOD 4 lengths. In order to ac-

complish the data alignment, the

Am79C978 controller simply in-

serts two bytes of random data at

the beginning of the receive pack-

et (i.e., before the ISO 8802-3

(IEEE/ANSI 802.3) destination

address field). The MCNT field

reported to the receive descriptor

will not include the extra two

bytes.

This bit is always read/write ac-

cessible. RCVALGN is cleared by

H_RESET or S_RESET and is

not affected by STOP.

CSR124: Test Register 1

This register is used to place the Am79C978 controller

into various test modes. The Runt Packet Accept is the

only user accessible test mode. All other test modes are

for AMD internal use only.

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