AM79C978VCSLASHW datasheet(147/261 Pages) AMD

147 / 261 page

Am79C978

147

This bit is always read/write ac-

cessible. LEDPE is cleared to 0

by H_RESET and is unaffected

by S_RESET or by setting the

STOP bit.

11-9

RES

Reserved locations. Written and

read as zeros.

APROMWE Address PROM Write Enable.

The Am79C978 controller con-

tains a shadow RAM on board for

storage of the first 16 bytes load-

ed from the serial EEPROM.

Accesses to Address PROM I/O

Resources will be directed toward

this RAM. When APROMWE is

set to 1, then write access to the

shadow RAM will be enabled.

This bit is always read/write ac-

cessible. APROMWE is cleared

to 0 by H_RESET and is unaffect-

ed by S_RESET or by setting the

STOP bit.

INTLEVEL

Interrupt Level. This bit allows the

interrupt output signals to be pro-

grammed

for

level

edge-

sensitive applications.

When INTLEVEL is cleared to 0,

the INTA pin is configured for

level-sensitive

applications.

this mode, an interrupt request is

signaled by a low level driven on

the INTA pin by the Am79C978

controller. When the interrupt is

cleared, the INTA pin is tri-stated

by the Am79C978 controller and

allowed to be pulled to a high lev-

el by an external pullup device.

This mode is intended for sys-

tems which allow the interrupt

signal to be shared by multiple

devices.

When INTLEVEL is set to 1, the

INTA pin is configured for edge-

sensitive

applications.

this

mode, an interrupt request is sig-

naled by a high level driven on

the INTA pin by the Am79C978

controller. When the interrupt is

cleared, the INTA pin is driven to

a low level by the Am79C978

controller. This mode is intended

for systems that do not allow in-

terrupt channels to be shared by

multiple devices.

INTLEVEL should not be set to 1

when the Am79C978 controller is

used in a PCI bus application.

This bit is always read/write ac-

cessible. INTLEVEL is cleared to

0 by H_RESET and is unaffected

by S_RESET or by setting the

STOP bit.

6-3

RES

Reserved locations. Written as

zeros and read as undefined.

2-0

RES

Reserved locations. Written and

read as zeros.

BCR4: LED0 Status

BCR4 controls the function(s) that the LED0 pin dis-

plays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabled functions. BCR4 defaults to

Link Status (LNKST) with pulse stretcher enabled

(PSE = 1) and is fully programmable.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED0 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED0 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

LEDOUT

This bit indicates the current

(non-stretched) value of the LED

output pin. A value of 1 in this bit

indicates that the OR of the en-

abled signals is true.

The logical value of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

This bit is read accessible al-

ways. This bit is read only; writes

have no effect. LEDOUT is unaf-

fected by H_RESET, S_RESET,

or STOP.

LEDPOL

LED Polarity. When this bit has

the value 0, then the LED pin will

AM79C978VC/W 数据表(PDF) 147 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 147 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AM79C978VC/W 数据表(PDF) 147 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 147 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载