AM79C978VCSLASHW datasheet(140/261 Pages) AMD

140 / 261 page

140

Am79C978

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. XMTFW is

set to a value of 00b (16 bytes) af-

ter H_RESET or S_RESET and

is unaffected by STOP.

7-0

DMATC[7:0] DMA Transfer Counter. Writing

and reading to this field has no ef-

fect.

Use

MAX_LAT

and

MIN_GNT in the PCI configura-

tion space.

CSR82: Transmit Descriptor Address Pointer

Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

TXDAPL

Contains the lower 16 bits of the

transmit descriptor address cor-

responding to the last buffer of

the previous transmit frame. If the

previous transmit frame did not

use buffer chaining, then TXDA-

PL contains the lower 16 bits of

the previous frame’s transmit de-

scriptor address.

When both the STOP or SPND

bits are cleared, this register is

updated by the Am79C978 con-

troller immediately before a trans-

mit descriptor write.

Read accessible always. Write

accessible through the PXDAL

bits (CSR60) when the STOP or

SPND bit is set. TXDAPL is set to

0 by H_RESET and are unaffect-

ed by S_RESET or STOP.

CSR84: DMA Address Register Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

DMABAL

This register contains the lower

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABAL register is undefined

until the first Am79C978 control-

ler DMA operation.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR85: DMA Address Register Upper

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

DMABAU

This register contains the upper

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABAU register is undefined

until the first Am79C978 control-

ler DMA operation.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR86: Buffer Byte Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-12 RES

Reserved. Read and written with

ones.

11-0

DMABC

DMA Byte Count Register. Con-

tains the two's complement of the

current size of the remaining

transmit

or receive

buffer in

bytes. This register is increment-

ed by the Bus Interface Unit. The

Table 34.

Transmit Watermark Programming

XMTFW[1:0]

Bytes Available

108

Reserved

AM79C978VC/W 数据表(PDF) 140 Page - Advanced Micro Devices

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