AM79C978VCSLASHW datasheet(139/261 Pages) AMD

139 / 261 page

Am79C978

139

transmit frame. When the entire

frame is in the MAC Transmit

FIFO, transmission will start re-

gardless of the value in XMTSP.

If the network interface is operat-

ing in half-duplex mode, regard-

less of XMTSP, the FIFO will not

internally overwrite its data until

at least 64 bytes (or the entire

frame if shorter than 64 bytes)

have been transmitted onto the

network. This ensures that for

collisions within the slot time win-

dow, transmit data need not be

rewritten to the Transmit FIFO,

and retries will be handled auton-

omously by the MAC. If the Dis-

able Retry feature is enabled, or if

the network is operating in full-du-

plex mode, the Am79C978 con-

troller

can

overwrite

the

beginning of the frame as soon as

the data is transmitted, because

no collision handling is required in

these modes.

Note that when the SRAM is be-

ing used, if the NOUFLO bit

(BCR18, bit 11) is set to 1, there

is the additional restriction that

the complete transmit frame must

be DMA’d into the Am79C978

controller and reside within a

combination of the Bus Transmit

FIFO, the SRAM, and the MAC

Transmit FIFO.

When the SRAM is used and

SRAM_SIZE > 0, there is a re-

striction that the number of bytes

written is a combination of bytes

written into the Bus Transmit

FIFO and the MAC Transmit

FIFO. The Am79C978 controller

supports a mode that will wait un-

til a full packet is available before

commencing with the transmis-

sion of preamble. This mode is

useful in a system where high la-

tencies cannot be avoided. See

Table 33.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. XMTSP is

set to a value of 01b (64 bytes) af-

ter H_RESET or S_RESET and

is unaffected by STOP.

Table 33.

Transmit Start Point Programming

9-8

XMTFW[1:0] Transmit FIFO Watermark. XMT-

FW specifies the point at which

transmit

DMA

requested,

based upon the number of bytes

that could be written to the Trans-

mit FIFO without FIFO overflow.

Transmit DMA is requested at

any time when the number of

bytes specified by XMTFW could

be written to the FIFO without

causing Transmit FIFO overflow

and the internal microcode en-

gine has reached a point where

the Transmit FIFO is checked to

determine if DMA servicing is re-

quired.

When operating in the NO-SRAM

mode (no SRAM enabled) and

SRAM_SIZE is set to 0, the Bus

Transmit FIFO and the MAC

Transmit FIFO operate like a sin-

gle FIFO and the watermark val-

ue selected by XMTFW[1:0] sets

the number of FIFO byte loca-

tions that must be available in the

FIFO before receive DMA is re-

quested.

When operating with the SRAM,

the Bus Transmit FIFO and the

MAC Transmit FIFO operate in-

dependently on the bus side and

MAC side of the SRAM, respec-

tively. In this case, the watermark

value set by XMTFW[1:0] sets the

number of FIFO byte locations

that must be available in the Bus

Transmit FIFO. See Table 34

XMTSP[1:0]

SRAM_SIZE

Bytes Written

128

220 max

128

Full Packet

Full Packet when

NOUFLO bit is set

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