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AN2014

Power supply loss and application reset

6.2

Power supply loss

Non-volatile memory data integrity of is a key condition as applications rely on these stored

values, mainly at system start up Power loss is critical for an EEPROM device when a Write

instruction is being issued or executed. In this event, the on-going write request or the

internal write process in the EEPROM may not have been completed, leading to data

corruption and data inconsistency.

6.2.1

Hardware recommendations

Application designer will find below some guidelines and recommendations to handle in the

best conditions power supply loss on systems designed with STMicroelectronics EEPROM

memories.

The power supply must designed in such a way that power loss is detected and backup

supply is supplied for a time allowing safe emergency ending of the system operations. The

list below gives some useful elements to build a robust power management system:

•

use voltage regulators including an output voltage sensor. It gives power loss

information to the Master before the supply is too low for system operation.

•

use available MCU features such as the Auxiliary Voltage Detector and External

Voltage Detector pin to create a delay between the detection of the low voltage and the

system reset.

•

use diodes, bipolar transistors or analog switches to create specific areas with backup

power capacitors.

The extra delay time gained should be used either to allow the EEPROM to complete any

on-going write process or to allow the Master to finish or interrupt safely the current

communication with the EEPROM. In a running application it is not possible to distinguish

these two possibilities, therefore the below recommendations must be considered all

together.

6.2.2

Supply voltage energy tank capacitor

In case of inadvertent power loss, applications are very often faced with the situation where

the EEPROM is operating while power supply is falling down.

It is not recommended to operate the device and in particular to initiate write operations

when the device is undergoing steady VCC transitions. ST EEPROM devices can however

handle write cycles during smooth power supply transitions. A power supply transition is

considered smooth when it allows a complete write cycle to be completed while VCC is

continuously falling or rising within the authorized VCC range. Taking advantage of this

possibility, a power backup capacitor can be designed to allow for the EEPROM to complete

its on-going self-timed write operation in case of inadvertent power loss.

The capacitor value is calculated so as to allow for the full write cycle to be executed:

•

l is the EEPROM supply current (ICC max)

•

t is the EEPROM write time (tW)

•

U is the voltage drop from the nominal value to VCC min of the EEPROM

Q = C × U = I × t => C = (l × t) / U

For instance:

C = (3 mA × 5 ms) / 2 V = 7.5 µF

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