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Choosing a suitable EEPROM for your application

AN2014

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Choosing a suitable EEPROM for your application

ST EEPROM products offer a very high quality level as they are produced with a mature

process and benefit from an efficient testing coverage on each single production part.

Nevertheless, the reliability on EEPROM products is also closely linked to the way they are

controlled in the end application. The aim of the following chapters is to provide a set of

recommendations to significantly improve the reliability and robustness in the end

application.

In the case of automotive applications, ST strongly recommends the use of products that

are classified as automotive grade, that is, devices referenced as MXXxxx-125 (previous

generation) and MXXxxx-A125/A145 (new generation with improved features). These

devices are designed to satisfy the most stringent quality requirements and are tested with

STMicroelectronics’ High Reliability Certified Flow (described in Quality Note, QNEE9801).

2.1

Choosing a memory type suited to the task to be performed

EEPROM devices are particularly suited to the tasks of code traceability and parameter

storage. The Serial protocol offers the best compromise of performance versus cost where

the access time is not critical.

2.2

Choosing an appropriate memory interface

ST is specialized in Serial Access EEPROMs, which are based on three main protocols: I²C,

SPI and MICROWIRE (see Table 1).

Fundamental requirements such as noise immunity, ESD, latchup and cycling Endurance

are basic features of each ST Serial EEPROM device (independent from the protocol used).

The choice of the most appropriate Serial EEPROM depends mainly on the hardware

resources of the master and on the architecture built around it. See the following:

•

The I2C bus offers a 2-wire protocol working at a maximum clock rate of 1 MHz and so

is preferred when the hardware resources are limited and the data rate is not a

constraint at all. The multiple slave configuration requires no extra hardware and is

managed by software.

•

The SPI bus and MICROWIRE bus are 4-wire protocols allowing higher communication

speed (speed is determined by each manufacturer design and technology). The

number of slaves is unlimited but N slaves require N additional master I/Os for each

chip select line. Both SPI and MICROWIRE bus can be reduced to only 3 wires

providing that the D and Q pins are tied together to a bidirectional I/O.

Data Write protection is different for each protocol family and is also a key factor when

selecting the memory interface. I2C products offer only hardware Write protection while SPI

and MICROWIRE products provide both hardware and software protection. Refer to

Section 5.3: Write protection.

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