AN2014 datasheet(64/65 Pages) STMICROELECTRONICS

64 / 65 page

Revision history

AN2014

64/65

DocID10701 Rev 10

31-Mar-2014

Modified Introduction and Conclusions.

Updated clock rate data in Table 1.

Text updated throughout the document, but more specifically:

– Chapter 2

– Section 3.1.3: ST EEPROM ESD protection

– Section 3.3.1: Power-up and power-on-reset sequence

– Section 4.1.1: Chip enable (E0, E1, E2)

– Section 4.1.2: Serial data (SDA)

– Section 4.1.3: Serial clock (SCL)

– Section 4.1.4: Write control (WC)

– Section 4.1.5: Recommended I2C EEPROM connections

– Section 4.2.2: Write Protect (W)

– Section 4.2.3: Serial Data input (D) and Serial Clock (C)

– Section 4.2.5: Serial Data output (Q)

– Section 5.4.2: Data redundancy

– Section 5.5: Cycling endurance and data retention

– Section 5.5.1: Cycling and data retention qualification procedures

– Section 5.5.2: Optimal cycling with ECC

– Section 5.5.3: Cycling and temperature dependence

– Section 5.5.5: Overall number of write cycles

– Section 6.3: Robust software and default operating mode

Changed Figure 39: Write cycling versus temperature.

Added specific values relating to process letter K.

17-Feb-2015

Updated Section 4.1.3: Serial clock (SCL), Section 5.3.1: Software write

protection and Section 5.5.4: Defining the application cycling strategy.

Updated Note below Figure 10 and Footnote 1 of Figure 29.

Modified Figures 21, 22, 25, 32, 39, 44, 45 and 46.

Other text updates throughout the document, without any context change.

Table 11. Document revision history (continued)

Date

Revision

Changes

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