AN2014 datasheet(30/65 Pages) STMICROELECTRONICS

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Hardware considerations

AN2014

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DocID10701 Rev 10

Figure 24. Write Protect input W

4.2.3

Serial Data input (D) and Serial Clock (C)

The Serial Data Input (D) and Serial Clock (C) signals are connected to a CMOS Schmitt

trigger input buffer and should be controlled by push-pull buffers (from the SPI master bus).

An external pull-down resistor on Serial Clock (C) signal will prevent “out-of-specification”

configurations like simultaneous rising edges on S and C when the Master releases the SPI

bus (violation of the tSHCH and tCHSH timings). An external pull-down resistor on the Serial

Data Input (D) (see Figure 27: Recommended SPI connections - robust design) will optimize

the signal control and the device standby current.

The pull-down resistor value on C is optimized if its value is larger than the pull-up resistor

value on the Chip Select (S) line. In this case, if the SPI bus is released (HiZ state), the Chip

Select (S) line goes high faster than the Clock (C) line goes low and so deselects the device

before the Clock signal crosses the input buffer trigger point (around VCC/2).

The input pin leakage is negligible, typically a few nA. The input schematic, including the

protection circuit, does not offer any open path to the VSS or VCC.

Note:

If the Clock (C) line cannot be pulled down (and must be pulled up due to other system

constraints), it is recommended to choose a lower pull-up resistor value (resistor value at

least three times lower) than the pull-up resistor value on the Chip Select (S) line. Moreover,

the "out-of-specification" configuration can also be minimized by connecting the Hold

(HOLD) pin to the reset signal (active low) of the Master: if the Master leaves the SPI bus in

high impedance, the Hold (HOLD) line goes low, locking the Clock to a low level (if already

low), thus preventing the occurrence of a rising edge on both the Clock and Chip Select

lines (this prevents the violation of the tCHSH and tSHCH timings).

4.2.4

Hold (HOLD)

The Hold (HOLD) is a CMOS Schmitt trigger input buffer used to pause communication. It

should be driven by a push-pull buffer (SPI master bus) for a better timing control, or tied

directly to VCC if unused. The hold pin cannot be left floating. The Hold input can be set

before the EEPROM power up and can remain high after power down. The Hold input will

not sink a current even if a voltage higher than VCC is applied to it.

The input pin leakage is negligible, typically a few nA. The input schematic, including the

protection circuit, does not offer any open path to the VSS or VCC (see Figure 23: Chip

Select, Clock, Data, Hold input pins).

Ai11066

W pin

ESD/EOS Protection

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