AN2014 datasheet(62/65 Pages) STMICROELECTRONICS

62 / 65 page

Revision history

AN2014

62/65

DocID10701 Rev 10

Revision history

Table 11. Document revision history

Date

Revision

Changes

28-Oct-2005

Initial release.

15-May-2006

Section 1.1.3: Cycling limit of EEPROM cells, Section 5.2.1: Page mode,

Section 5.4.1: The checksum, Section 5.5: Cycling endurance and data

retention, Section 6.1: Application reset, Section 6.2: Power supply loss

modified. Small text changes.

26-Oct-2006

Small text changes. Figure 14: Power-up and Figure 39 modified

(paragraph added to explain Figure 39). Table 5: Calculation rules for pull-

up resistor on SDA and Note 1 modified.

Note modified below Figure 22. Section 5.4: Data integrity modified.

Section 6.2.2: Supply voltage energy tank capacitor modified. “General

recommendation applying to all EEPROM products” paragraph removed

and content transferred to Section 3.3.1 on page 21.

15-Jan-2007

Small text changes.

In the SPI family the S pin must remain above VIH = 0.7VCC during power-

up (see Section 4.2.1: Chip Select (S)) and Write Protect (W) behavior

specified.

Pull-up and pull-down resistances discussed in Section 4.2.3: Serial Data

input (D) and Serial Clock (C) (SPI) and Section 4.3.2: Serial Data (D) and

Serial Clock (C) (MICROWIRE).

Pull-down resistor value on C modified and pull-down resistor added to D

line in Figure 27: Recommended SPI connections - robust design and

Figure 31: Recommended MICROWIRE connections - robust design.

Maximum C2 value modified in Figure 32: PCB decoupling.

26-Jun-2008

Small text changes. Section 3.3.2: Stabilized power supply voltage,

Section 3.3.1: Power-up and power-on-reset sequence and Section 4.1.5:

Recommended I2C EEPROM connections clarified.

Section 4.4.3: Communication lines removed.

Section 6.1: Application reset modified, Figure 40: I2C bus enters the high

impedance state (Master reset), Figure 41: SPI bus enters the high

impedance state (Master reset) and Figure 42: MICROWIRE bus enters

the high impedance state (Master reset) modified.

04-Feb-2010

Removed reference to application note AN1001 in Section 2.2: Choosing

an appropriate memory interface.

Updated POR threshold in Table 3: Typical POR threshold values.

Updated programming time in Section 5.1: EEPROM electrical

parameters. Updated Section 5.5.1: Cycling and data retention

qualification procedures and Section 5.5.3: Cycling and temperature

dependence. Added Section 5.5.2: Optimal cycling with ECC.

AN2014 数据表(PDF) 62 Page - STMicroelectronics

AN2014 数据表(HTML) 62 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

数据表下载