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AN2014 数据表(PDF) 42 Page - STMicroelectronics |
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AN2014 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 65 page ![]() Software considerations AN2014 42/65 DocID10701 Rev 10 5.3.2 Hardware write protection By default the hardware write protection feature should be set and the time during which the device is left unprotected should be limited to the time required to issue and execute Write instructions. The hardware write protection is very effective against parasitic or hazardous instructions transiting on the interface bus. Also use the hardware write protection features during Power-up, Power-down and normal operation (Refer to the Hardware considerations). • The WC pin in I²C products protects the entire array. • The W pin protects the entire array by resetting the Write Enable Latch (WEL) bit in 1 Kbit to 4 Kbit SPI products whereas it protects the non-volatile bits of the Status Register in 8 Kbit to 2 Mbit SPI products. It is recommended to change the state of the Write Protect pin only if no data transfer or program cycle is in progress. The Write Protect and Write Control pins should be controlled with very conservative timings: • 1 clock cycle time clearance (with no data transfer) before the select (or start) event. • 1 clock cycle time clearance (with no data transfer) after the deselect (or stop) event. • Wait for the write cycle (tW) completion before changing the protection. This conservative sequence will not affect the communication speed but will ensure the safe operation of the products (see Figure 36 and Figure 37). The Write Protect signal (W for SPI, WC for I²C) is glitch sensitive and a short (parasitic) pulse could cause a write request to be aborted. This feature can also be of great help in emergency situations like power loss or Master reset. See the Power supply loss and application reset section for details. Figure 36. .Recommended use of the WC pin in I²C products Figure 37. Recommended use of the W pin in SPI products Clearance 1 Clock Period Clearance 1 Clock Period ai10921 WC START + WRITE +ADDRESS + DATA + STOP tW < 5ms SDA Clearance 1 Clock Period Clearance 1 Clock Period ai10922 W WRITE +ADDRESS + DATA tW < 5ms SDA S WREN Polling |
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