AN2014 datasheet(50/65 Pages) STMICROELECTRONICS

50 / 65 page

Power supply loss and application reset

AN2014

50/65

DocID10701 Rev 10

Figure 40. I2C bus enters the high impedance state (Master reset)

It is important to note that when the Master is reset and releases the I2C bus, the commonly

used pull-up resistors on the SCL and SDA pins (case1) increase the probability of sourcing

an erroneous Stop condition. The recommended I2C connections for a robust design are

also detailed in Section 4.1.5.

When the transmission of an I2C bus command is interrupted before completion (before the

Stop condition), the EEPROM is paused in its communication until the Master is able to take

again the control of the I2C bus. Before accessing the EEPROM, the Master must follow the

sequence below:

•

Master must first send a re-synchronization sequence to the EEPROM. It consists of 9

START conditions + 1 STOP condition to re-initialize the internal state machine and

deselect the device safely. Refer to AN1471 for any help to implement this sequence.

•

Master must check that EEPROM is ready (no write cycle in progress) by sending a

data polling sequence. Refer to Section 5.2.2: Data polling.

Note:

For the first read access to the EEPROM, it is recommended to define the internal address

pointer with a Random Read instruction as a current Address Read does not change/define

the address pointer value.

These recommendations allow to maximize the control on the EEPROM in case of

inadvertent Master reset.

AN2014 数据表(PDF) 50 Page - STMicroelectronics