 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AN2014 数据表(PDF) 29 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
AN2014 数据表(HTML) 29 Page - STMicroelectronics |
|
|
29 / 65 page  DocID10701 Rev 10 29/65 AN2014 Hardware considerations 64 4.2 SPI family (M95xxx devices) 4.2.1 Chip Select (S) Chip Select (S) is a CMOS Schmitt trigger input buffer protected from ESD and EOS spikes, as shown in Figure 23. Chip Select (S) must never be left floating, and must be constantly held at VCC outside the communication slots. It is strongly recommended to add a pull-up resistor to ensure a high level on the Chip Select pin at any time and in particular during power-up, power-down and during the reset phase of the master, since, during these phases, the master usually leaves its I/Os in high impedance. The pull-up resistance should be calculated as a function of the bus capacitive load so that the voltage on the S pin always remains above VIH = 0.7VCC during power-up. The input pin leakage is negligible, typically a few nA. The input schematics, including the protection circuit, does not offer any open path to the VSS or VCC. Note: To filter out wrong selections, the M95xxx devices are internally selected only when the following two conditions are met: S falling edge and S remains low. Figure 23. Chip Select, Clock, Data, Hold input pins 4.2.2 Write Protect (W) The Write Protect (W) signal is a CMOS input used to enable or disable Write protection. To ensure the write protection at Power-up and Power-down, its default state should be low. It is therefore recommended to add a pull-down resistor on /W (which value must be smaller than the pull-up resistor on S line), to optimize write protection latency in cases where the controller releases the SPI bus in high impedance (power-up, power-down and Master reset phases). In this case the Write Protect (W) line goes low before the Chip select (S) line goes high (since the time constant of the W pull-down resistor is smaller than the time constant of the S pull-up resistor, see Section 4.2.6: Recommended SPI EEPROM connections), thus preventing the potential execution of an ongoing write command. Note: For 1 Kbit to 4 Kbit SPI devices, the /W protects the Write to memory and for devices of density above 8 Kbits, the /W protects the Write in the Status Register. The input pin leakage is negligible, typically a few nA. The input schematic, including the protection circuit, does not offer any open path to VSS or VCC. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
