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AN2014

Software considerations

5.4

Data integrity

In several applications, the implementation of a data integrity strategy is mandatory. Several

strategies are possible, but whatever the solution used, extra memory density is required to

hold the extra data.

5.4.1

The checksum

It is perhaps the more commonly used method to prevent data loss, data corruption and

poor communication. It consists in computing a checksum of the data to write and in storing

it into the memory array as an additional data byte. Checksums are particularly suitable for

the secure communication of parameters that are often read and updated.

To give applications more robustness, more elaborated checksum routines like Error Code

Correction can also be used to correct detected errors.

5.4.2

Data redundancy

Data redundancy is also a good way of preventing data loss and data corruption. Data

redundancy is more particularly adapted to the read-only data stored in the EEPROM.

Typically, this kind of data is programmed once during module manufacturing and then only

read during the whole application lifetime. As the data is never refreshed, there is a higher

probability of facing a retention loss. With redundancy, there is a backup on each read-only

byte.

The efficiency of redundancy depends on the physical structure of the memory. As

described previously, the memory array is organized as rows (or pages) and columns where

each byte location (address) is the intersection of a row and a column. Redundant data

should not share the same row (or page) and column (byte location inside one page) but

should be located at physically independent addresses (see Figure 38).

The following rules should be kept in mind by the designer:

•

The redundant data should not be located in the same page as the reference data

page.

•

The address of the duplicated data should differ from original address by at least 1 bit

in the column address and 1 bit in the page address (see Table 9: Column and page

address bits according to page length).

Note:

More detailed information on memory array, data scrambling and address decoding are

available on request.

Table 9. Column and page address bits according to page length

Page length

Column address bits

Page address bits

Page of 16 bytes

4 LSB bits

All other MSB bits

Page of 32 bytes

5 LSB bits

All other MSB bits

Page of 64 bytes

6 LSB bits

All other MSB bits

Page of 128 bytes

7 LSB bits

All other MSB bits

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