AN2014 datasheet(14/65 Pages) STMICROELECTRONICS

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EEPROM cell and memory array architecture

AN2014

14/65

DocID10701 Rev 10

1.2.2

Decoding architecture

To address a single byte in a full array, decoding circuits are necessary. One logical address

is associated with one byte location. The address bits are inserted serially into a Shift

same time, to perform the decoding and addressing. The row decoder decodes and brings

correct biasing to a single row line. As one or more bytes of the same row can be

programmed at the same time, the column decoder decodes one or more column(s), and a

RAM buffer memorizes the data to write, and enables the right path for Cg-line and Bit-line

biasing.

Figure 11. Decoding block diagram

1.2.3

Intrinsic electrical stress induced by programming

Whatever the data value to be programmed and whether the request is made by byte or

page, all high-voltage circuits(a) are stressed by HiV (a high voltage ranging between 15 and

18V). In particular, the internal nodes of the charge pump can see voltages equal to

HiV + VCC (that is as much as 23 V). All circuits that receive and carry HiV (ramp generator,

regulation, decoding, latches) are submitted to higher stress than active low voltage

transistors. The overall time during which the high voltage circuits are active is relatively

short compared to the product lifetime (10ms x 1Mcycles = 10000 seconds => less than 3

hours).

A standard ST EEPROM device includes a few hundred high voltage transistors, for low

memory density products (1Kbit). This number can rise to a few thousand for high memory

density products (1Mbit).

AI10225

Address Shift Register

Column

Decoder

Bit-line and Cg-line Latches: RAM Buffer

Row

Decoder

Array

Cg-lines and Bit-lines

Row-lines

Read/Write Analog

Voltages

Serial Input

MSB Address Bits

LSB Address Bits

a. The high voltage is required to Erase and program an EEPROM cell.

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