AN2014 datasheet(49/65 Pages) STMICROELECTRONICS

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AN2014

Power supply loss and application reset

6.1

Application reset

During the application runtime, the Master may be reset by some external reset condition

like a watchdog timer, a power supply monitor, or an ESD. In such case, the serial bus is not

controlled (it is left floating) while the power supply stays stable at its nominal value. When

this occurs, the challenge is to either control the completion of the ongoing write cycle or to

stop the communication with the EEPROM.

When the Master is reset, the EEPROM can be:

•

deselected in Standby mode. This is the best and safest case. The EEPROM was in

the Idle state and will keep this state if the hardware connections are correct. The

EEPROM will be ready to accept any new command when the Master is restarted.

•

deselected while performing an internal write cycle. It is not a problem as at the end of

the self-timed internal write process, the device returns to the standby state. Note that if

the Master restarts while the EEPROM is still programming, the Master has to check

that the EEPROM is ready by issuing a write cycle polling sequence.

•

selected while receiving a command or answering to a Read command. This case has

to be handled specifically according to the EEPROM protocol family.

The solutions discussed hereafter concern only the case where an EEPROM is selected.

The aim of these recommendations is to properly stop the communication with the device in

order to avoid further potential disturbances.

6.1.1

I2C family

The basic principle to protect an I2C transaction is to avoid issuing a Stop condition when a

reset occurs. This is because a Stop condition can be decoded as the trigger of an

undesired write cycle if the command was a Write and if this Stop condition occurs right at

the end of a data byte.

On the other hand, the Start condition is a safe event as it resets the internal state machine

and as the Start is decoded by a specific logic block that is always active.

Smart connections on the I2C bus lines help to avoid erroneous Stop conditions when the

Master is reset (I2C bus in high impedance), as described in Figure 40: I2C bus enters the

high impedance state (Master reset).

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