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AN2014 数据表(PDF) 33 Page - STMicroelectronics |
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AN2014 数据表(HTML) 33 Page - STMicroelectronics |
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33 / 65 page  DocID10701 Rev 10 33/65 AN2014 Hardware considerations 64 4.3 MICROWIRE® family (M93Cxxx and M93Sxxx devices) 4.3.1 Chip Select (S) The Chip Select (S) input pin is connected to a CMOS Schmitt trigger input buffer (see Figure 28: Chip Select, Clock, Data input pins). It is recommended that the master bus controls the Chip select (S) with a push-pull buffer. S must never be left floating. It is therefore strongly recommended to add a pull-down resistor to ensure a low level on the Chip Select input at any time, so that the device remains deselected, including during periods when the S line is in high impedance, such as power-up, power-down and the reset phase of the Master. The input pin leakage is negligible, typically a few nA. The input schematic, including the protection circuit, does not offer any open path to the VSS or VCC. Figure 28. Chip Select, Clock, Data input pins 4.3.2 Serial Data (D) and Serial Clock (C) Serial Data (D) and Serial Clock (C) input pins are connected to a CMOS Schmitt trigger input buffer (see Figure 28).It is recommended the Master bus controls them with a push- pull buffer. An external pull-down resistor (RPD) on a Serial Clock (C) signal will prevent from an “out-of-specification” configuration such as a clock rising edge while Chip Select goes low when the Master releases the bus (Hi-Z state, violation of the tSLCH timing)). An external pull-down resistor on Serial Data Input (D) will optimize signal control and standby current. Pull-down resistor values on Serial Clock (C) and Serial Data (D) are optimized if they are at least three times bigger than the pull-down value on the Chip Select (S) line. In this case, if the SPI bus is released, the Chip Select (S) line goes Low faster than the Clock (C) line goes low, and so, deselects the device before the Clock signal crosses the input buffer trigger point (area around VCC/2 is always sensitive). If the Clock (C) line cannot be pulled down and must be pulled up due to other system constraints, it is recommended to choose a weaker pull-up value (at least three times weaker) than the pull-down value on Chip Select (S). The input pin leakage is typically a few nA. The input schematic, including the protection circuit, does not offer any open path to the VSS or VCC. Ai11727 S, C, D ESD/EOS Protection Glitch Filter Schmitt trigger |
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