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TAS2553 数据表(PDF) 31 Page - Texas Instruments |
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TAS2553 数据表(HTML) 31 Page - Texas Instruments |
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31 / 58 page  DOUT IVCLKIN DATA HI-Z td(DATA) td(HI-Z) HI-Z DATA DATA TAS2553 www.ti.com SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 Figure 50. DOUT Timing in PDM Mode (Data on IVCLKIN Low) Table 10. DOUT Timing in PDM Mode(1) IOVDD=1.8V(2) IOVDD=3.3V PARAMETER UNIT MIN MAX MIN MAX td(DATA) IVCLKIN to DOUT delay 30 30 ns td(HI-Z) IVCLKIN to high impedance state delay 6 6 ns (1) All timing specifications are measured at characterization but not tested at final test. (2) All specifications at 25°C, IOVDD = 1.8 V 7.5 Register Map The TAS2553 I2C address is 0x40 (7-bit) when ADDR = 0 and 0x41 (7-bit) when ADDR = 1. See the General I2C Operation section for more details. 7.5.1 Register Map Summary REGISTER READ/WRITE DEFAULT FUNCTION DEC HEX 0 0x00 R/W 0x00 Device Status Register 1 0x01 R/W 0x22 Configuration Register 1 2 0x02 R/W 0xFF Configuration Register 2 3 0x03 R/W 0x80 Configuration Register 3 4 0x04 R/W 0x00 DOUT Tristate Mode 5 0x05 R/W 0x00 Serial Interface Control Register 1 6 0x06 R/W 0x00 Serial Interface Control Register 2 7 0x07 R/W 0xC0 Output Data Register 8 0x08 R/W 0x10 PLL Control Register 1 9 0x09 R/W 0x00 PLL Control Register 2 10 0x0A R/W 0x00 PLL Control Register 3 11 0x0B R/W 0x8F Battery Tracking Inflection Point Register 12 0x0C R/W 0x80 Battery Tracking Slope Control Register 13 0x0D R/W 0xBE Limiter Level Control Register 14 0x0E R/W 0x08 Limiter Attack Rate and Hysteresis Time 15 0x0F R/W 0x05 Limiter Release Rate 16 0x10 R/W 0x00 Limiter Integration Count Control 17 0x11 R/W 0x01 PDM Configuration Register 18 0x12 R/W 0x00 PGA Gain Register 19 0x13 R/W 0x40 Class-D Edge Rate Control Register 20 0x14 R/W 0x00 Boost Auto-Pass Through Control Register 21 0x15 R/W 0x00 Reserved 22 0x16 R 0x00 Version Number 23 0x17 R/W 0x00 Reserved Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: TAS2553 |
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