TAS2553_15 datasheet(27/58 Pages) TI

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LD(n)

LD (n+1)

WORD

CLOCK

BIT

CLOCK

DATA

RD(n)

LEFT CHANNEL

RIGHT CHANNEL

LD(n) = n'th sample of left channel data

RD(n) = n'th sample of right channel data

TAS2553

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SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

Table 8. DSP Timing in Slave Mode (see Figure 43)

IOVDD=1.8V

IOVDD=3.3V

PARAMETER

UNIT

MIN

MAX

MIN

MAX

tH(BCLK)

BCLK high period

tL(BCLK)

BCLK low period

ts(WS)

(WS)

th(WS)

WCLK hold

td(DO-WS)

WCLK to DOUT delay (For LJF Mode only)

ts(DI)

DIN setup

th(DI)

DIN hold

Rise time

Fall time

7.4.2 TDM Mode

Time-division multiplexing (TDM) allows two or more devices to share a common DIN connection and a common

DOUT connection. Using TDM mode, all devices transmit their DOUT data in user-specified sub-frames within

one WCLK period. When one device transmits its DOUT information, the other devices place their DOUT

terminals in a high impedance tri-state mode.

TDM mode is useable with I2S, LJF, RJF, and DSP interface modes. Refer to the respective sections for a

description of how to set the TAS2553 into those modes. TDM cannot be used with PDM mode. This is because

the PDM requires a continuous stream of samples from one data source.

Use Register 0x06 to set the clock cycle offset from WCLK to the MSB. Each data bit is valid on the falling edge

of the bit clock. Set Register 0x04, D(2) = 1 to force DOUT into tri-state when it is not transmitting data. This

allows DOUT terminals from multiple TAS2553 devices to share a common wire to the host.

Figure 44. Timing Diagram for I2S in TDM Mode with Offset=2

For TDM mode, the number of bit-clocks per frame should be less than the programmed word-length of the data.

Also the programmed offset value should be less than the number of bit-clocks per frame by at least the

programmed word-length of the data.

Figure 45 shows how to configure the TAS2553 with the TI codec, AIC3254, with both devices sharing DIN and

DOUT

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