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TAS2553 数据表(PDF) 17 Page - Texas Instruments |
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TAS2553 数据表(HTML) 17 Page - Texas Instruments |
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17 / 58 page ![]() P 2 J.D 0.5 K K MCLK IVCLKIN BCLK 1.8 MHz Internal Register 0x01, D(5:4) PLL_CLKIN PLL_CLK Register 0x09, D(7) 0 1 10 00 01 11 Registers 0x08 - 0x0A 24.5760 MHz (for 16-bit, FS = 48 kHz) 22.5792 MHz (for 16-bit, FS = 44.1 kHz) ÷ 8 PLL_BYPASS To DAC clock input IVCLKIN BCLK MCLK 01 00 10 11 PDM_CLK Register 0x11, D(1:0) 0 = falling edge 1 = rising edge Register 0x11, D(2) Register 0x03, D(6) 0 = PDM 1 = I2S / LJF / RJF / DSP 0 1 I2S_OUT_SEL I-V sense ADC clock generation TAS2553 www.ti.com SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 Feature Description (continued) Figure 28. Clock Distribution Tree 7.3.8 Gain Settings The TAS2553 has one gain register for both analog input and digital input (DAC output) gain. A mux selects only one of these inputs for the Class-D speaker amplifier. The analog and digital inputs cannot be mixed together. The full-scale DAC output voltage is the same as the maximum analog input voltage (for less than 1% THD): 1 VRMS, or 1.4 VPEAK. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: TAS2553 |
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