TAS2553_15 datasheet(32/58 Pages) TI

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TAS2553

SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

www.ti.com

READ/WRITE

DEFAULT

FUNCTION

DEC

HEX

0x18

0x00

Reserved

0x19

0x00

VBAT Data Register

7.5.2 Register 0x00: Device Status Register

This register uses latched faults. The fault bits are clear on write. Read-only commands retain the latched value

of the fault bit.

BIT

NAME

READ/WRITE

DEFAULT DESCRIPTION

7-6

R/W

Reserved. Write only default values.

PLL_OUT_OF_LOCK

R/W

PLL lock

0 = PLL is locked

1 = PLL is not locked

4-2

R/W

Reserved. Write only default values.

CLASSD_ILIM

R/W

Class-D over-current

0 = Normal operation

1 = Class-D output current limit has been exceeded

THERMAL

R/W

Thermal limit

0 = Normal operation

1 = Limit exceeded

7.5.3 Register 0x01: Configuration Register 1

BIT

NAME

READ/WRITE

DEFAULT DESCRIPTION

7-6

R/W

Reserved. Write only default values.

5-4

PLL_SRC

R/W

PLL Input

00 = MCLK

01 = BCLK

10 = IVCLKIN

11 = 1.8 MHz fixed internal oscillator

R/W

Reserved. Write only default values.

MUTE

R/W

Triggers mute of Class-D channel controller.

0 = Not muted

1 = Muted

SWS

R/W

Software shutdown. When high shuts down all blocks and places part in low

power mode. THIS BIT MUST BE SET TO ZERO ONLY AFTER THE

DEVICE CONFIGURATION IS COMPLETE.

DEV_RESET

R/W

Synchronous reset of all digital registers & control circuitry.

7.5.4 Register 0x02: Configuration Register 2

BIT

NAME

READ/WRITE

DEFAULT

DESCRIPTION

CLASSD_EN

R/W

Class D Enable

BOOST_EN

R/W

Boost Enable

APT_EN

R/W

Auto Pass-Thru Enable

RESERVED

R/W

Reserved. Write only default values.

PLL_EN

R/W

PLL Enable

LIM_EN

R/W

Battery Tracking AGC Enable

IVSENSE_EN

R/W

I/V Sense Enable

RESERVED

R/W

1(1)

Reserved. MUST BE WRITTEN TO ZERO DURING CONFIGURATION

SEQUENCE as shown in Initialization.

(1)

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