TAS2553_15 datasheet(35/58 Pages) TI

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TAS2553

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SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

7.5.9 Register 0x07: Output Data Register

This register sets the output data for DOUT. Most systems will simply set L_DATA_OUT to transmit output

current data and R_DATA_OUT to transmit voltage data. Other data is available, like VBAT voltage, VBOOST

voltage, and PGA gain.

Bit 5 is a dual-purpose bit. If I2S_OUT_SEL = 0 (Register 0x03, Bit 6) and the PDM_DATA_SEL bits are set to

transmit only I-Data or V-Data, then Bit 5 dictates if that data is transmitted on the clock rising edge or falling

edge. This allows two TAS2553 devices in PDM mode to tie their DOUT lines together and connect to the host

digital mic input. In this configuration, each device broadcasts its output current or output voltage information –

one on the rising edge of the clock, the other on the falling edge. This is a simple interface technique that does

not require programming the host for TDM-interface mode.

BIT

NAME

READ / WRITE

DEFAULT

DESCRIPTION

7-6

PDM_DATA_SEL

R/W

PDM Data Select

These bits are operative only if I2S_OUT_SEL = 0 for PDM mode (see

00 - I Data Only - Select Ch1 or Ch2 with bit[5]

01 - V Data Only - Select Ch1 or Ch2 with bit[5]

10 - I/V Data (Ch1/2)

11 - V/I Data (Ch1/2)

5-3

R_DATA_OUT

R/W

000

Serial Interface Data, Right Channel

Bit 5 is a dual-purpose bit, depending on the state of I2S_OUT_SEL

(Register 0x03, Bit 6).

If I2S_OUT_SEL = 0 and PDM_DATA_SEL = 00 or 01 (for single-

channel PDM output mode), then Bit 5 will select whether data is

transmitted on the rising or falling edge of the clock.

0xx = Falling Edge (Ch 1)

1xx = Rising Edge (Ch 2)

If I2S_OUT_SEL = 1, then Bits 5-3 have the same function as

L_DATA_OUT. Read the description in L_DATA_OUT for requirements

on BCLK and WORD_LENGTH.

000 = I Data (16'b)

001 = V Data (16'b)

010 = VBAT Data (8'b)

011 = VBOOST Data (8'b)

100 = PGA Gain (5'b)

101 = I Data, V Data (32'b)

110 = VBAT, VBOOST, PGA Gain (21'b)

111 = Disabled (Hi-Z)

NOTE: For VBAT and VBOOST, the device must be in a mode that uses

this information, such as Battery Tracking AGC.

2-0

L_DATA_OUT

R/W

000

Serial Interface Data, Left Channel

Users must provide enough BCLK cycles per WCLK frame to shift all the

data out. If there are additional BCLK cycles per WCLK frame beyond

the WORD_LENGTH setting, the data line will be HI-Z if

SDOUT_TRISTATE (Register 0x04, Bit 3) is set to 1; otherwise the data

line will be held low for the extra BCLK cycles.

Users must also program a sufficient WORD_LENGTH setting. If

selected data contains fewer bits than WORD_LENGTH setting, the

extra bits will be 0's.

000 = I Data (16'b)

001 = V Data (16'b)

010 = VBAT Data (8'b)

011 = VBOOST Data (8'b)

100 = PGA Gain (5'b)

101 = I Data, V Data (32'b)

110 = VBAT, VBOOST, PGA Gain (21'b)

111 = Disabled (Hi-Z)

NOTE: For VBAT and VBOOST, the device must be in a mode that uses

this information, such as Battery Tracking AGC.

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