TAS2553_15 datasheet(20/58 Pages) TI

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TAS2553

SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

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Table 3. Attack Time Selection (continued)

ATTACK TIME REGISTER

ATTACK TIME

BYTE: ATK_TIME[2:0]

( µS / STEP)

101

1770

110

2120

111

2470

Table 4. Release Time Selection

RELEASE TIME REGISTER

RELEASE TIME

RELEASE TIME REGISTER

RELEASE TIME

BYTE: REL_TIME[3:0]

( MS / STEP)

BYTE: REL_TIME[4:0]

(MS / STEP)

0000

1000

890

0001

155

1001

995

0010

260

1010

1100

0011

365

1011

1205

0100

470

1100

1310

0101

575

1101

1415

0110

680

1110

1520

0111

785

1111

1625

7.4 Device Functional Modes

7.4.1 Audio Digital I/O Interface

Audio data is transferred between the host processor and the TAS2553 via the digital audio data serial interface,

or audio bus. The audio bus on this device is very flexible, including left or right-justified data options, support for

I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible

master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a

system directly.

The audio bus of the TAS2553 can be configured for left or right-justified, I2S, DSP, or TDM modes of operation,

where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes

are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Register 0x05, D(1:0). In

addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for

flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame,

and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to

the maximum of the selected ADC and DAC sampling frequencies.

The bit clock is used to clock in and clock out the digital audio data across the serial bus. This signal can be

programmed to generate variable clock pulses by controlling the bit-clock multiply-divide factor in Registers 0x08

through 0x10. The number of bit-clock pulses in a frame may need adjustment to accommodate various word-

lengths as well as to support the case when multiple TAS2553 devices may share the same audio bus.

The TAS2553 also includes a feature to offset the position of start of data transfer with respect to the word-clock.

This offset is in number of bit-clocks and is programmed in Register 0x06.

To place the DOUT line into a Hi-Z (3-state) condition during all bit clocks when valid data is not being sent, set

audio data begins, time-division multiplexing (TDM) can be accomplished. This enables the use of multiple

devices on a single audio serial data bus. When the audio serial data bus is powered down while configured in

master mode, the terminals associated with the interface are put into a Hi-Z output state.

7.4.1.1 Right-Justified Mode

Set Register 0x03, D(6) = 0 and Register 0x05, D(3:2) = 10 to place the TAS2553 audio interface into right-

justified mode. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock

preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of

the bit clock preceding the rising edge of the word clock.

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