TAS2553_15 datasheet(16/58 Pages) TI

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PLL_CLKIN

1.1 MHz

9.2 MHz

PLL_CLKIN

512 kHz

12.288 MHz

0.5 PLL _ CLKI

PLL _ C K

N J.

ACK

Acknowledge

I2CDeviceAddressand

Read/WriteBit

R/W

R/W ACK

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

LastDataByte

ACK

FirstDataByte

RepeatStart

Condition

Not

Acknowledge

I2CDeviceAddressand

Read/WriteBit

OtherDataBytes

D0 ACK

Acknowledge

TAS2553

SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

www.ti.com

Feature Description (continued)

7.3.6 Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes

are transmitted by the TAS2553 to the master device as shown in Figure 27. With the exception of the last data

byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 27. Multiple-Byte Read Transfer

7.3.7 PLL

The TAS2553 has an on-chip PLL to generate the clock frequency for the audio DAC and I-V sensing ADCs. The

programmability of the PLL allows operation from a wide variety of clocks that may be available in the system.

The PLL input supports clocks varying from 512 kHz to 24.576 MHz and is register programmable to enable

generation of required sampling rates with fine resolution. Set Register 0x02, D(3) = 1 to activate the PLL. When

the PLL is enabled, the PLL output clock PLL_CLK is:

(1)

J = 4, 5, 6, … 96

D = 0, 1, 2, ... 9999

P = 0,1

Choose J, D, P such that PLL_CLK = 22.5792 MHz (44.1ksps sampling rate) or 24.5760 MHz (48ksps sampling

rate). Program variable J in Register 0x08, D(6:0). Program variable D in Register 0x09, D(5:0) and Register

0x0A, D(7:0). The default value for D is 0. Program variable P in Register 0x08, D(7). The default value for P is

use MCLK, 01 to use BCLK, and 10 to use IVCLKIN.

There is also an option to use a 1.8 MHz internal oscillator for PLL_CLKIN. This is useful for systems using the

analog inputs and the I-V sense data returning to a host processor via PDM mode interface. Set Register 0x01,

D(5:4) = 11 to use the 1.8 MHz internal oscillator.

To bypass the PLL, set Register 0x09, D(7) = 1. Deactivate the PLL by setting Register 0x02, D(3) = 0.

When the PLL is enabled, the following conditions must be satisfied:

•

If D = 0, the PLL clock input (PLL_CLKIN) must satisfy:

•

If D

≠ 0, the PLL clock input (PLL_CLKIN) must satisfy:

Figure 28 shows the clock distribution tree and the registers required to set the audio input DAC and the I-V

sense ADC.

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