TAS2553_15 datasheet(6/58 Pages) TI

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TAS2553

SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

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Electrical Characteristics (continued)

VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, EN = IOVDD, SWS = 0, Gain = 15 dB, ERC = 14 ns, RL = 8 Ω + 33 µH, 48 kHz

sample rate for digital input (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

THD+N = 1%, VBAT = 3.0 V

2.8

Max Output Power, 8-

Ω Load

THD+N = 1%, VBAT = 3.6 V

2.8

Output Impedance in Shutdown

EN = 0 V

Analog/digital input measured from time

Startup Time

when device is taken out of software

shutdown

Measured from time when device is

Shutdown Time

µS

programmed in software shutdown mode

INPUT SECTION

Full-scale DAC output

All digital interface modes

1.0

VRMS

Maximum analog input voltage

1.0

VRMS

EN = IOVDD, Amplifier active

Input impedance (terminals AIN+,

RIN

AIN-)

EN = 0 V, In shutdown

CURRENT SENSE

Peak current which will give full scale

Current Sense Full Scale

1.4

APEAK

digital output

Current Sense Accuracy

IOUT = 354 mARMS (1 W)

Current Sense Offset

Input referred

0.0029

Current Sense Gain Error

0.09

THD+N

Distortion + Noise

Po = 1.0W (Load = 8

Ω + 33 µH)

0.17%

VOLTAGE SENSE

Peak voltage which will give full scale

Voltage Sense Full Scale

8.5

VPEAK

digital output

Voltage Sense Accuracy

VOUT = 2.83 Vrms (1W)

2.2%

Voltage Sense Offset

Input referred

1.45

Voltage Sense Gain Error

-0.20

THD+N

Distortion + Noise

Po = 1.0 W (Load = 8

Ω + 33μH)

0.08%

INTERFACE

FMCLK

MCLK frequency

0.512

49.15

MHz

FPDM

PDM Clock (IVCLK) Frequency Range

1.636

3.25

MHz

PDM Clock (IVCLK) Duty Cycle

PDMDC

40%

60%

Range

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